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<div class="header">
  <div class="headertitle"><div class="title">m33.h</div></div>
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<div class="contents">
<div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
<div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
<div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_M33_H</span></div>
<div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_M33_H</span></div>
<div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span> </div>
<div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
<div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="preprocessor">#include &quot;hardware/regs/m33.h&quot;</span></div>
<div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span> </div>
<div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33</span></div>
<div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">//</span></div>
<div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
<div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.</span></div>
<div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span><span class="comment">//</span></div>
<div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
<div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
<div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span> </div>
<div class="line"><a id="l00026" name="l00026"></a><span class="lineno">   26</span><span class="preprocessor">#if defined(__riscv) &amp;&amp; PICO_FORBID_ARM_HEADERS_ON_RISCV</span></div>
<div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span><span class="preprocessor">#error &quot;Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1&quot;</span></div>
<div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span><span class="preprocessor">#endif</span></div>
<div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span> </div>
<div class="line"><a id="l00030" name="l00030"></a><span class="lineno"><a class="line" href="structm33__hw__t.html">   30</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    <span class="comment">// (Description copied from array index 0 register M33_ITM_STIM0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span>    _REG_(M33_ITM_STIM0_OFFSET) <span class="comment">// M33_ITM_STIM0</span></div>
<div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span>    <span class="comment">// ITM Stimulus Port Register 0</span></div>
<div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span>    <span class="comment">// 0xffffffff [31:0]  STIMULUS     (0x00000000) Data to write to the Stimulus Port FIFO, for forwarding...</span></div>
<div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span>    io_rw_32 itm_stim[32];</div>
<div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span> </div>
<div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span>    uint32_t _pad0[864];</div>
<div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span> </div>
<div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span>    _REG_(M33_ITM_TER0_OFFSET) <span class="comment">// M33_ITM_TER0</span></div>
<div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span>    <span class="comment">// Provide an individual enable bit for each ITM_STIM register</span></div>
<div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span>    <span class="comment">// 0xffffffff [31:0]  STIMENA      (0x00000000) For STIMENA[m] in ITM_TER*n, controls whether...</span></div>
<div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span>    io_rw_32 itm_ter0;</div>
<div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span> </div>
<div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span>    uint32_t _pad1[15];</div>
<div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span> </div>
<div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span>    _REG_(M33_ITM_TPR_OFFSET) <span class="comment">// M33_ITM_TPR</span></div>
<div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>    <span class="comment">// Controls which stimulus ports can be accessed by unprivileged code</span></div>
<div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span>    <span class="comment">// 0x0000000f [3:0]   PRIVMASK     (0x0) Bit mask to enable tracing on ITM stimulus ports</span></div>
<div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    io_rw_32 itm_tpr;</div>
<div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span> </div>
<div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>    uint32_t _pad2[15];</div>
<div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span> </div>
<div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>    _REG_(M33_ITM_TCR_OFFSET) <span class="comment">// M33_ITM_TCR</span></div>
<div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    <span class="comment">// Configures and controls transfers through the ITM interface</span></div>
<div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>    <span class="comment">// 0x00800000 [23]    BUSY         (0) Indicates whether the ITM is currently processing events</span></div>
<div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span>    <span class="comment">// 0x007f0000 [22:16] TRACEBUSID   (0x00) Identifier for multi-source trace stream formatting</span></div>
<div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>    <span class="comment">// 0x00000c00 [11:10] GTSFREQ      (0x0) Defines how often the ITM generates a global timestamp,...</span></div>
<div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span>    <span class="comment">// 0x00000300 [9:8]   TSPRESCALE   (0x0) Local timestamp prescaler, used with the trace packet...</span></div>
<div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    <span class="comment">// 0x00000020 [5]     STALLENA     (0) Stall the PE to guarantee delivery of Data Trace packets</span></div>
<div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span>    <span class="comment">// 0x00000010 [4]     SWOENA       (0) Enables asynchronous clocking of the timestamp counter</span></div>
<div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span>    <span class="comment">// 0x00000008 [3]     TXENA        (0) Enables forwarding of hardware event packet from the DWT...</span></div>
<div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span>    <span class="comment">// 0x00000004 [2]     SYNCENA      (0) Enables Synchronization packet transmission for a...</span></div>
<div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    <span class="comment">// 0x00000002 [1]     TSENA        (0) Enables Local timestamp generation</span></div>
<div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span>    <span class="comment">// 0x00000001 [0]     ITMENA       (0) Enables the ITM</span></div>
<div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span>    io_rw_32 itm_tcr;</div>
<div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span> </div>
<div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span>    uint32_t _pad3[27];</div>
<div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span> </div>
<div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span>    _REG_(M33_INT_ATREADY_OFFSET) <span class="comment">// M33_INT_ATREADY</span></div>
<div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span>    <span class="comment">// Integration Mode: Read ATB Ready</span></div>
<div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span>    <span class="comment">// 0x00000002 [1]     AFVALID      (0) A read of this bit returns the value of AFVALID</span></div>
<div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span>    <span class="comment">// 0x00000001 [0]     ATREADY      (0) A read of this bit returns the value of ATREADY</span></div>
<div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span>    io_ro_32 int_atready;</div>
<div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span> </div>
<div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span>    uint32_t _pad4;</div>
<div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span> </div>
<div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span>    _REG_(M33_INT_ATVALID_OFFSET) <span class="comment">// M33_INT_ATVALID</span></div>
<div class="line"><a id="l00078" name="l00078"></a><span class="lineno">   78</span>    <span class="comment">// Integration Mode: Write ATB Valid</span></div>
<div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span>    <span class="comment">// 0x00000002 [1]     AFREADY      (0) A write to this bit gives the value of AFREADY</span></div>
<div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span>    <span class="comment">// 0x00000001 [0]     ATREADY      (0) A write to this bit gives the value of ATVALID</span></div>
<div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span>    io_rw_32 int_atvalid;</div>
<div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span> </div>
<div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span>    uint32_t _pad5;</div>
<div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span> </div>
<div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span>    _REG_(M33_ITM_ITCTRL_OFFSET) <span class="comment">// M33_ITM_ITCTRL</span></div>
<div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span>    <span class="comment">// Integration Mode Control Register</span></div>
<div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span>    <span class="comment">// 0x00000001 [0]     IME          (0) Integration mode enable bit - The possible values are: ...</span></div>
<div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span>    io_rw_32 itm_itctrl;</div>
<div class="line"><a id="l00089" name="l00089"></a><span class="lineno">   89</span> </div>
<div class="line"><a id="l00090" name="l00090"></a><span class="lineno">   90</span>    uint32_t _pad6[46];</div>
<div class="line"><a id="l00091" name="l00091"></a><span class="lineno">   91</span> </div>
<div class="line"><a id="l00092" name="l00092"></a><span class="lineno">   92</span>    _REG_(M33_ITM_DEVARCH_OFFSET) <span class="comment">// M33_ITM_DEVARCH</span></div>
<div class="line"><a id="l00093" name="l00093"></a><span class="lineno">   93</span>    <span class="comment">// Provides CoreSight discovery information for the ITM</span></div>
<div class="line"><a id="l00094" name="l00094"></a><span class="lineno">   94</span>    <span class="comment">// 0xffe00000 [31:21] ARCHITECT    (0x23b) Defines the architect of the component</span></div>
<div class="line"><a id="l00095" name="l00095"></a><span class="lineno">   95</span>    <span class="comment">// 0x00100000 [20]    PRESENT      (1) Defines that the DEVARCH register is present</span></div>
<div class="line"><a id="l00096" name="l00096"></a><span class="lineno">   96</span>    <span class="comment">// 0x000f0000 [19:16] REVISION     (0x0) Defines the architecture revision of the component</span></div>
<div class="line"><a id="l00097" name="l00097"></a><span class="lineno">   97</span>    <span class="comment">// 0x0000f000 [15:12] ARCHVER      (0x1) Defines the architecture version of the component</span></div>
<div class="line"><a id="l00098" name="l00098"></a><span class="lineno">   98</span>    <span class="comment">// 0x00000fff [11:0]  ARCHPART     (0xa01) Defines the architecture of the component</span></div>
<div class="line"><a id="l00099" name="l00099"></a><span class="lineno">   99</span>    io_ro_32 itm_devarch;</div>
<div class="line"><a id="l00100" name="l00100"></a><span class="lineno">  100</span> </div>
<div class="line"><a id="l00101" name="l00101"></a><span class="lineno">  101</span>    uint32_t _pad7[3];</div>
<div class="line"><a id="l00102" name="l00102"></a><span class="lineno">  102</span> </div>
<div class="line"><a id="l00103" name="l00103"></a><span class="lineno">  103</span>    _REG_(M33_ITM_DEVTYPE_OFFSET) <span class="comment">// M33_ITM_DEVTYPE</span></div>
<div class="line"><a id="l00104" name="l00104"></a><span class="lineno">  104</span>    <span class="comment">// Provides CoreSight discovery information for the ITM</span></div>
<div class="line"><a id="l00105" name="l00105"></a><span class="lineno">  105</span>    <span class="comment">// 0x000000f0 [7:4]   SUB          (0x4) Component sub-type</span></div>
<div class="line"><a id="l00106" name="l00106"></a><span class="lineno">  106</span>    <span class="comment">// 0x0000000f [3:0]   MAJOR        (0x3) Component major type</span></div>
<div class="line"><a id="l00107" name="l00107"></a><span class="lineno">  107</span>    io_ro_32 itm_devtype;</div>
<div class="line"><a id="l00108" name="l00108"></a><span class="lineno">  108</span> </div>
<div class="line"><a id="l00109" name="l00109"></a><span class="lineno">  109</span>    _REG_(M33_ITM_PIDR4_OFFSET) <span class="comment">// M33_ITM_PIDR4</span></div>
<div class="line"><a id="l00110" name="l00110"></a><span class="lineno">  110</span>    <span class="comment">// Provides CoreSight discovery information for the ITM</span></div>
<div class="line"><a id="l00111" name="l00111"></a><span class="lineno">  111</span>    <span class="comment">// 0x000000f0 [7:4]   SIZE         (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00112" name="l00112"></a><span class="lineno">  112</span>    <span class="comment">// 0x0000000f [3:0]   DES_2        (0x4) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00113" name="l00113"></a><span class="lineno">  113</span>    io_ro_32 itm_pidr4;</div>
<div class="line"><a id="l00114" name="l00114"></a><span class="lineno">  114</span> </div>
<div class="line"><a id="l00115" name="l00115"></a><span class="lineno">  115</span>    _REG_(M33_ITM_PIDR5_OFFSET) <span class="comment">// M33_ITM_PIDR5</span></div>
<div class="line"><a id="l00116" name="l00116"></a><span class="lineno">  116</span>    <span class="comment">// Provides CoreSight discovery information for the ITM</span></div>
<div class="line"><a id="l00117" name="l00117"></a><span class="lineno">  117</span>    <span class="comment">// 0x00000000 [31:0]  ITM_PIDR5    (0x00000000) </span></div>
<div class="line"><a id="l00118" name="l00118"></a><span class="lineno">  118</span>    io_rw_32 itm_pidr5;</div>
<div class="line"><a id="l00119" name="l00119"></a><span class="lineno">  119</span> </div>
<div class="line"><a id="l00120" name="l00120"></a><span class="lineno">  120</span>    _REG_(M33_ITM_PIDR6_OFFSET) <span class="comment">// M33_ITM_PIDR6</span></div>
<div class="line"><a id="l00121" name="l00121"></a><span class="lineno">  121</span>    <span class="comment">// Provides CoreSight discovery information for the ITM</span></div>
<div class="line"><a id="l00122" name="l00122"></a><span class="lineno">  122</span>    <span class="comment">// 0x00000000 [31:0]  ITM_PIDR6    (0x00000000) </span></div>
<div class="line"><a id="l00123" name="l00123"></a><span class="lineno">  123</span>    io_rw_32 itm_pidr6;</div>
<div class="line"><a id="l00124" name="l00124"></a><span class="lineno">  124</span> </div>
<div class="line"><a id="l00125" name="l00125"></a><span class="lineno">  125</span>    _REG_(M33_ITM_PIDR7_OFFSET) <span class="comment">// M33_ITM_PIDR7</span></div>
<div class="line"><a id="l00126" name="l00126"></a><span class="lineno">  126</span>    <span class="comment">// Provides CoreSight discovery information for the ITM</span></div>
<div class="line"><a id="l00127" name="l00127"></a><span class="lineno">  127</span>    <span class="comment">// 0x00000000 [31:0]  ITM_PIDR7    (0x00000000) </span></div>
<div class="line"><a id="l00128" name="l00128"></a><span class="lineno">  128</span>    io_rw_32 itm_pidr7;</div>
<div class="line"><a id="l00129" name="l00129"></a><span class="lineno">  129</span> </div>
<div class="line"><a id="l00130" name="l00130"></a><span class="lineno">  130</span>    _REG_(M33_ITM_PIDR0_OFFSET) <span class="comment">// M33_ITM_PIDR0</span></div>
<div class="line"><a id="l00131" name="l00131"></a><span class="lineno">  131</span>    <span class="comment">// Provides CoreSight discovery information for the ITM</span></div>
<div class="line"><a id="l00132" name="l00132"></a><span class="lineno">  132</span>    <span class="comment">// 0x000000ff [7:0]   PART_0       (0x21) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00133" name="l00133"></a><span class="lineno">  133</span>    io_ro_32 itm_pidr0;</div>
<div class="line"><a id="l00134" name="l00134"></a><span class="lineno">  134</span> </div>
<div class="line"><a id="l00135" name="l00135"></a><span class="lineno">  135</span>    _REG_(M33_ITM_PIDR1_OFFSET) <span class="comment">// M33_ITM_PIDR1</span></div>
<div class="line"><a id="l00136" name="l00136"></a><span class="lineno">  136</span>    <span class="comment">// Provides CoreSight discovery information for the ITM</span></div>
<div class="line"><a id="l00137" name="l00137"></a><span class="lineno">  137</span>    <span class="comment">// 0x000000f0 [7:4]   DES_0        (0xb) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00138" name="l00138"></a><span class="lineno">  138</span>    <span class="comment">// 0x0000000f [3:0]   PART_1       (0xd) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00139" name="l00139"></a><span class="lineno">  139</span>    io_ro_32 itm_pidr1;</div>
<div class="line"><a id="l00140" name="l00140"></a><span class="lineno">  140</span> </div>
<div class="line"><a id="l00141" name="l00141"></a><span class="lineno">  141</span>    _REG_(M33_ITM_PIDR2_OFFSET) <span class="comment">// M33_ITM_PIDR2</span></div>
<div class="line"><a id="l00142" name="l00142"></a><span class="lineno">  142</span>    <span class="comment">// Provides CoreSight discovery information for the ITM</span></div>
<div class="line"><a id="l00143" name="l00143"></a><span class="lineno">  143</span>    <span class="comment">// 0x000000f0 [7:4]   REVISION     (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00144" name="l00144"></a><span class="lineno">  144</span>    <span class="comment">// 0x00000008 [3]     JEDEC        (1) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00145" name="l00145"></a><span class="lineno">  145</span>    <span class="comment">// 0x00000007 [2:0]   DES_1        (0x3) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00146" name="l00146"></a><span class="lineno">  146</span>    io_ro_32 itm_pidr2;</div>
<div class="line"><a id="l00147" name="l00147"></a><span class="lineno">  147</span> </div>
<div class="line"><a id="l00148" name="l00148"></a><span class="lineno">  148</span>    _REG_(M33_ITM_PIDR3_OFFSET) <span class="comment">// M33_ITM_PIDR3</span></div>
<div class="line"><a id="l00149" name="l00149"></a><span class="lineno">  149</span>    <span class="comment">// Provides CoreSight discovery information for the ITM</span></div>
<div class="line"><a id="l00150" name="l00150"></a><span class="lineno">  150</span>    <span class="comment">// 0x000000f0 [7:4]   REVAND       (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00151" name="l00151"></a><span class="lineno">  151</span>    <span class="comment">// 0x0000000f [3:0]   CMOD         (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00152" name="l00152"></a><span class="lineno">  152</span>    io_ro_32 itm_pidr3;</div>
<div class="line"><a id="l00153" name="l00153"></a><span class="lineno">  153</span> </div>
<div class="line"><a id="l00154" name="l00154"></a><span class="lineno">  154</span>    <span class="comment">// (Description copied from array index 0 register M33_ITM_CIDR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00155" name="l00155"></a><span class="lineno">  155</span>    _REG_(M33_ITM_CIDR0_OFFSET) <span class="comment">// M33_ITM_CIDR0</span></div>
<div class="line"><a id="l00156" name="l00156"></a><span class="lineno">  156</span>    <span class="comment">// Provides CoreSight discovery information for the ITM</span></div>
<div class="line"><a id="l00157" name="l00157"></a><span class="lineno">  157</span>    <span class="comment">// 0x000000ff [7:0]   PRMBL_0      (0x0d) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00158" name="l00158"></a><span class="lineno">  158</span>    io_ro_32 itm_cidr[4];</div>
<div class="line"><a id="l00159" name="l00159"></a><span class="lineno">  159</span> </div>
<div class="line"><a id="l00160" name="l00160"></a><span class="lineno">  160</span>    _REG_(M33_DWT_CTRL_OFFSET) <span class="comment">// M33_DWT_CTRL</span></div>
<div class="line"><a id="l00161" name="l00161"></a><span class="lineno">  161</span>    <span class="comment">// Provides configuration and status information for the DWT unit, and used to control features of the unit</span></div>
<div class="line"><a id="l00162" name="l00162"></a><span class="lineno">  162</span>    <span class="comment">// 0xf0000000 [31:28] NUMCOMP      (0x7) Number of DWT comparators implemented</span></div>
<div class="line"><a id="l00163" name="l00163"></a><span class="lineno">  163</span>    <span class="comment">// 0x08000000 [27]    NOTRCPKT     (0) Indicates whether the implementation does not support trace</span></div>
<div class="line"><a id="l00164" name="l00164"></a><span class="lineno">  164</span>    <span class="comment">// 0x04000000 [26]    NOEXTTRIG    (0) Reserved, RAZ</span></div>
<div class="line"><a id="l00165" name="l00165"></a><span class="lineno">  165</span>    <span class="comment">// 0x02000000 [25]    NOCYCCNT     (1) Indicates whether the implementation does not include a...</span></div>
<div class="line"><a id="l00166" name="l00166"></a><span class="lineno">  166</span>    <span class="comment">// 0x01000000 [24]    NOPRFCNT     (1) Indicates whether the implementation does not include...</span></div>
<div class="line"><a id="l00167" name="l00167"></a><span class="lineno">  167</span>    <span class="comment">// 0x00800000 [23]    CYCDISS      (0) Controls whether the cycle counter is disabled in Secure state</span></div>
<div class="line"><a id="l00168" name="l00168"></a><span class="lineno">  168</span>    <span class="comment">// 0x00400000 [22]    CYCEVTENA    (1) Enables Event Counter packet generation on POSTCNT underflow</span></div>
<div class="line"><a id="l00169" name="l00169"></a><span class="lineno">  169</span>    <span class="comment">// 0x00200000 [21]    FOLDEVTENA   (1) Enables DWT_FOLDCNT counter</span></div>
<div class="line"><a id="l00170" name="l00170"></a><span class="lineno">  170</span>    <span class="comment">// 0x00100000 [20]    LSUEVTENA    (1) Enables DWT_LSUCNT counter</span></div>
<div class="line"><a id="l00171" name="l00171"></a><span class="lineno">  171</span>    <span class="comment">// 0x00080000 [19]    SLEEPEVTENA  (0) Enable DWT_SLEEPCNT counter</span></div>
<div class="line"><a id="l00172" name="l00172"></a><span class="lineno">  172</span>    <span class="comment">// 0x00040000 [18]    EXCEVTENA    (1) Enables DWT_EXCCNT counter</span></div>
<div class="line"><a id="l00173" name="l00173"></a><span class="lineno">  173</span>    <span class="comment">// 0x00020000 [17]    CPIEVTENA    (0) Enables DWT_CPICNT counter</span></div>
<div class="line"><a id="l00174" name="l00174"></a><span class="lineno">  174</span>    <span class="comment">// 0x00010000 [16]    EXTTRCENA    (0) Enables generation of Exception Trace packets</span></div>
<div class="line"><a id="l00175" name="l00175"></a><span class="lineno">  175</span>    <span class="comment">// 0x00001000 [12]    PCSAMPLENA   (1) Enables use of POSTCNT counter as a timer for Periodic...</span></div>
<div class="line"><a id="l00176" name="l00176"></a><span class="lineno">  176</span>    <span class="comment">// 0x00000c00 [11:10] SYNCTAP      (0x2) Selects the position of the synchronization packet...</span></div>
<div class="line"><a id="l00177" name="l00177"></a><span class="lineno">  177</span>    <span class="comment">// 0x00000200 [9]     CYCTAP       (0) Selects the position of the POSTCNT tap on the CYCCNT counter</span></div>
<div class="line"><a id="l00178" name="l00178"></a><span class="lineno">  178</span>    <span class="comment">// 0x000001e0 [8:5]   POSTINIT     (0x1) Initial value for the POSTCNT counter</span></div>
<div class="line"><a id="l00179" name="l00179"></a><span class="lineno">  179</span>    <span class="comment">// 0x0000001e [4:1]   POSTPRESET   (0x2) Reload value for the POSTCNT counter</span></div>
<div class="line"><a id="l00180" name="l00180"></a><span class="lineno">  180</span>    <span class="comment">// 0x00000001 [0]     CYCCNTENA    (0) Enables CYCCNT</span></div>
<div class="line"><a id="l00181" name="l00181"></a><span class="lineno">  181</span>    io_rw_32 dwt_ctrl;</div>
<div class="line"><a id="l00182" name="l00182"></a><span class="lineno">  182</span> </div>
<div class="line"><a id="l00183" name="l00183"></a><span class="lineno">  183</span>    _REG_(M33_DWT_CYCCNT_OFFSET) <span class="comment">// M33_DWT_CYCCNT</span></div>
<div class="line"><a id="l00184" name="l00184"></a><span class="lineno">  184</span>    <span class="comment">// Shows or sets the value of the processor cycle counter, CYCCNT</span></div>
<div class="line"><a id="l00185" name="l00185"></a><span class="lineno">  185</span>    <span class="comment">// 0xffffffff [31:0]  CYCCNT       (0x00000000) Increments one on each processor clock cycle when DWT_CTRL</span></div>
<div class="line"><a id="l00186" name="l00186"></a><span class="lineno">  186</span>    io_rw_32 dwt_cyccnt;</div>
<div class="line"><a id="l00187" name="l00187"></a><span class="lineno">  187</span> </div>
<div class="line"><a id="l00188" name="l00188"></a><span class="lineno">  188</span>    uint32_t _pad8;</div>
<div class="line"><a id="l00189" name="l00189"></a><span class="lineno">  189</span> </div>
<div class="line"><a id="l00190" name="l00190"></a><span class="lineno">  190</span>    _REG_(M33_DWT_EXCCNT_OFFSET) <span class="comment">// M33_DWT_EXCCNT</span></div>
<div class="line"><a id="l00191" name="l00191"></a><span class="lineno">  191</span>    <span class="comment">// Counts the total cycles spent in exception processing</span></div>
<div class="line"><a id="l00192" name="l00192"></a><span class="lineno">  192</span>    <span class="comment">// 0x000000ff [7:0]   EXCCNT       (0x00) Counts one on each cycle when all of the following are...</span></div>
<div class="line"><a id="l00193" name="l00193"></a><span class="lineno">  193</span>    io_rw_32 dwt_exccnt;</div>
<div class="line"><a id="l00194" name="l00194"></a><span class="lineno">  194</span> </div>
<div class="line"><a id="l00195" name="l00195"></a><span class="lineno">  195</span>    uint32_t _pad9;</div>
<div class="line"><a id="l00196" name="l00196"></a><span class="lineno">  196</span> </div>
<div class="line"><a id="l00197" name="l00197"></a><span class="lineno">  197</span>    _REG_(M33_DWT_LSUCNT_OFFSET) <span class="comment">// M33_DWT_LSUCNT</span></div>
<div class="line"><a id="l00198" name="l00198"></a><span class="lineno">  198</span>    <span class="comment">// Increments on the additional cycles required to execute all load or store instructions</span></div>
<div class="line"><a id="l00199" name="l00199"></a><span class="lineno">  199</span>    <span class="comment">// 0x000000ff [7:0]   LSUCNT       (0x00) Counts one on each cycle when all of the following are...</span></div>
<div class="line"><a id="l00200" name="l00200"></a><span class="lineno">  200</span>    io_rw_32 dwt_lsucnt;</div>
<div class="line"><a id="l00201" name="l00201"></a><span class="lineno">  201</span> </div>
<div class="line"><a id="l00202" name="l00202"></a><span class="lineno">  202</span>    _REG_(M33_DWT_FOLDCNT_OFFSET) <span class="comment">// M33_DWT_FOLDCNT</span></div>
<div class="line"><a id="l00203" name="l00203"></a><span class="lineno">  203</span>    <span class="comment">// Increments on the additional cycles required to execute all load or store instructions</span></div>
<div class="line"><a id="l00204" name="l00204"></a><span class="lineno">  204</span>    <span class="comment">// 0x000000ff [7:0]   FOLDCNT      (0x00) Counts on each cycle when all of the following are true:...</span></div>
<div class="line"><a id="l00205" name="l00205"></a><span class="lineno">  205</span>    io_rw_32 dwt_foldcnt;</div>
<div class="line"><a id="l00206" name="l00206"></a><span class="lineno">  206</span> </div>
<div class="line"><a id="l00207" name="l00207"></a><span class="lineno">  207</span>    uint32_t _pad10;</div>
<div class="line"><a id="l00208" name="l00208"></a><span class="lineno">  208</span> </div>
<div class="line"><a id="l00209" name="l00209"></a><span class="lineno">  209</span>    _REG_(M33_DWT_COMP0_OFFSET) <span class="comment">// M33_DWT_COMP0</span></div>
<div class="line"><a id="l00210" name="l00210"></a><span class="lineno">  210</span>    <span class="comment">// Provides a reference value for use by watchpoint comparator 0</span></div>
<div class="line"><a id="l00211" name="l00211"></a><span class="lineno">  211</span>    <span class="comment">// 0xffffffff [31:0]  DWT_COMP0    (0x00000000) </span></div>
<div class="line"><a id="l00212" name="l00212"></a><span class="lineno">  212</span>    io_rw_32 dwt_comp0;</div>
<div class="line"><a id="l00213" name="l00213"></a><span class="lineno">  213</span> </div>
<div class="line"><a id="l00214" name="l00214"></a><span class="lineno">  214</span>    uint32_t _pad11;</div>
<div class="line"><a id="l00215" name="l00215"></a><span class="lineno">  215</span> </div>
<div class="line"><a id="l00216" name="l00216"></a><span class="lineno">  216</span>    _REG_(M33_DWT_FUNCTION0_OFFSET) <span class="comment">// M33_DWT_FUNCTION0</span></div>
<div class="line"><a id="l00217" name="l00217"></a><span class="lineno">  217</span>    <span class="comment">// Controls the operation of watchpoint comparator 0</span></div>
<div class="line"><a id="l00218" name="l00218"></a><span class="lineno">  218</span>    <span class="comment">// 0xf8000000 [31:27] ID           (0x0b) Identifies the capabilities for MATCH for comparator *n</span></div>
<div class="line"><a id="l00219" name="l00219"></a><span class="lineno">  219</span>    <span class="comment">// 0x01000000 [24]    MATCHED      (0) Set to 1 when the comparator matches</span></div>
<div class="line"><a id="l00220" name="l00220"></a><span class="lineno">  220</span>    <span class="comment">// 0x00000c00 [11:10] DATAVSIZE    (0x0) Defines the size of the object being watched for by Data...</span></div>
<div class="line"><a id="l00221" name="l00221"></a><span class="lineno">  221</span>    <span class="comment">// 0x00000030 [5:4]   ACTION       (0x0) Defines the action on a match</span></div>
<div class="line"><a id="l00222" name="l00222"></a><span class="lineno">  222</span>    <span class="comment">// 0x0000000f [3:0]   MATCH        (0x0) Controls the type of match generated by this comparator</span></div>
<div class="line"><a id="l00223" name="l00223"></a><span class="lineno">  223</span>    io_rw_32 dwt_function0;</div>
<div class="line"><a id="l00224" name="l00224"></a><span class="lineno">  224</span> </div>
<div class="line"><a id="l00225" name="l00225"></a><span class="lineno">  225</span>    uint32_t _pad12;</div>
<div class="line"><a id="l00226" name="l00226"></a><span class="lineno">  226</span> </div>
<div class="line"><a id="l00227" name="l00227"></a><span class="lineno">  227</span>    _REG_(M33_DWT_COMP1_OFFSET) <span class="comment">// M33_DWT_COMP1</span></div>
<div class="line"><a id="l00228" name="l00228"></a><span class="lineno">  228</span>    <span class="comment">// Provides a reference value for use by watchpoint comparator 1</span></div>
<div class="line"><a id="l00229" name="l00229"></a><span class="lineno">  229</span>    <span class="comment">// 0xffffffff [31:0]  DWT_COMP1    (0x00000000) </span></div>
<div class="line"><a id="l00230" name="l00230"></a><span class="lineno">  230</span>    io_rw_32 dwt_comp1;</div>
<div class="line"><a id="l00231" name="l00231"></a><span class="lineno">  231</span> </div>
<div class="line"><a id="l00232" name="l00232"></a><span class="lineno">  232</span>    uint32_t _pad13;</div>
<div class="line"><a id="l00233" name="l00233"></a><span class="lineno">  233</span> </div>
<div class="line"><a id="l00234" name="l00234"></a><span class="lineno">  234</span>    _REG_(M33_DWT_FUNCTION1_OFFSET) <span class="comment">// M33_DWT_FUNCTION1</span></div>
<div class="line"><a id="l00235" name="l00235"></a><span class="lineno">  235</span>    <span class="comment">// Controls the operation of watchpoint comparator 1</span></div>
<div class="line"><a id="l00236" name="l00236"></a><span class="lineno">  236</span>    <span class="comment">// 0xf8000000 [31:27] ID           (0x11) Identifies the capabilities for MATCH for comparator *n</span></div>
<div class="line"><a id="l00237" name="l00237"></a><span class="lineno">  237</span>    <span class="comment">// 0x01000000 [24]    MATCHED      (1) Set to 1 when the comparator matches</span></div>
<div class="line"><a id="l00238" name="l00238"></a><span class="lineno">  238</span>    <span class="comment">// 0x00000c00 [11:10] DATAVSIZE    (0x2) Defines the size of the object being watched for by Data...</span></div>
<div class="line"><a id="l00239" name="l00239"></a><span class="lineno">  239</span>    <span class="comment">// 0x00000030 [5:4]   ACTION       (0x2) Defines the action on a match</span></div>
<div class="line"><a id="l00240" name="l00240"></a><span class="lineno">  240</span>    <span class="comment">// 0x0000000f [3:0]   MATCH        (0x8) Controls the type of match generated by this comparator</span></div>
<div class="line"><a id="l00241" name="l00241"></a><span class="lineno">  241</span>    io_rw_32 dwt_function1;</div>
<div class="line"><a id="l00242" name="l00242"></a><span class="lineno">  242</span> </div>
<div class="line"><a id="l00243" name="l00243"></a><span class="lineno">  243</span>    uint32_t _pad14;</div>
<div class="line"><a id="l00244" name="l00244"></a><span class="lineno">  244</span> </div>
<div class="line"><a id="l00245" name="l00245"></a><span class="lineno">  245</span>    _REG_(M33_DWT_COMP2_OFFSET) <span class="comment">// M33_DWT_COMP2</span></div>
<div class="line"><a id="l00246" name="l00246"></a><span class="lineno">  246</span>    <span class="comment">// Provides a reference value for use by watchpoint comparator 2</span></div>
<div class="line"><a id="l00247" name="l00247"></a><span class="lineno">  247</span>    <span class="comment">// 0xffffffff [31:0]  DWT_COMP2    (0x00000000) </span></div>
<div class="line"><a id="l00248" name="l00248"></a><span class="lineno">  248</span>    io_rw_32 dwt_comp2;</div>
<div class="line"><a id="l00249" name="l00249"></a><span class="lineno">  249</span> </div>
<div class="line"><a id="l00250" name="l00250"></a><span class="lineno">  250</span>    uint32_t _pad15;</div>
<div class="line"><a id="l00251" name="l00251"></a><span class="lineno">  251</span> </div>
<div class="line"><a id="l00252" name="l00252"></a><span class="lineno">  252</span>    _REG_(M33_DWT_FUNCTION2_OFFSET) <span class="comment">// M33_DWT_FUNCTION2</span></div>
<div class="line"><a id="l00253" name="l00253"></a><span class="lineno">  253</span>    <span class="comment">// Controls the operation of watchpoint comparator 2</span></div>
<div class="line"><a id="l00254" name="l00254"></a><span class="lineno">  254</span>    <span class="comment">// 0xf8000000 [31:27] ID           (0x0a) Identifies the capabilities for MATCH for comparator *n</span></div>
<div class="line"><a id="l00255" name="l00255"></a><span class="lineno">  255</span>    <span class="comment">// 0x01000000 [24]    MATCHED      (0) Set to 1 when the comparator matches</span></div>
<div class="line"><a id="l00256" name="l00256"></a><span class="lineno">  256</span>    <span class="comment">// 0x00000c00 [11:10] DATAVSIZE    (0x0) Defines the size of the object being watched for by Data...</span></div>
<div class="line"><a id="l00257" name="l00257"></a><span class="lineno">  257</span>    <span class="comment">// 0x00000030 [5:4]   ACTION       (0x0) Defines the action on a match</span></div>
<div class="line"><a id="l00258" name="l00258"></a><span class="lineno">  258</span>    <span class="comment">// 0x0000000f [3:0]   MATCH        (0x0) Controls the type of match generated by this comparator</span></div>
<div class="line"><a id="l00259" name="l00259"></a><span class="lineno">  259</span>    io_rw_32 dwt_function2;</div>
<div class="line"><a id="l00260" name="l00260"></a><span class="lineno">  260</span> </div>
<div class="line"><a id="l00261" name="l00261"></a><span class="lineno">  261</span>    uint32_t _pad16;</div>
<div class="line"><a id="l00262" name="l00262"></a><span class="lineno">  262</span> </div>
<div class="line"><a id="l00263" name="l00263"></a><span class="lineno">  263</span>    _REG_(M33_DWT_COMP3_OFFSET) <span class="comment">// M33_DWT_COMP3</span></div>
<div class="line"><a id="l00264" name="l00264"></a><span class="lineno">  264</span>    <span class="comment">// Provides a reference value for use by watchpoint comparator 3</span></div>
<div class="line"><a id="l00265" name="l00265"></a><span class="lineno">  265</span>    <span class="comment">// 0xffffffff [31:0]  DWT_COMP3    (0x00000000) </span></div>
<div class="line"><a id="l00266" name="l00266"></a><span class="lineno">  266</span>    io_rw_32 dwt_comp3;</div>
<div class="line"><a id="l00267" name="l00267"></a><span class="lineno">  267</span> </div>
<div class="line"><a id="l00268" name="l00268"></a><span class="lineno">  268</span>    uint32_t _pad17;</div>
<div class="line"><a id="l00269" name="l00269"></a><span class="lineno">  269</span> </div>
<div class="line"><a id="l00270" name="l00270"></a><span class="lineno">  270</span>    _REG_(M33_DWT_FUNCTION3_OFFSET) <span class="comment">// M33_DWT_FUNCTION3</span></div>
<div class="line"><a id="l00271" name="l00271"></a><span class="lineno">  271</span>    <span class="comment">// Controls the operation of watchpoint comparator 3</span></div>
<div class="line"><a id="l00272" name="l00272"></a><span class="lineno">  272</span>    <span class="comment">// 0xf8000000 [31:27] ID           (0x04) Identifies the capabilities for MATCH for comparator *n</span></div>
<div class="line"><a id="l00273" name="l00273"></a><span class="lineno">  273</span>    <span class="comment">// 0x01000000 [24]    MATCHED      (0) Set to 1 when the comparator matches</span></div>
<div class="line"><a id="l00274" name="l00274"></a><span class="lineno">  274</span>    <span class="comment">// 0x00000c00 [11:10] DATAVSIZE    (0x2) Defines the size of the object being watched for by Data...</span></div>
<div class="line"><a id="l00275" name="l00275"></a><span class="lineno">  275</span>    <span class="comment">// 0x00000030 [5:4]   ACTION       (0x0) Defines the action on a match</span></div>
<div class="line"><a id="l00276" name="l00276"></a><span class="lineno">  276</span>    <span class="comment">// 0x0000000f [3:0]   MATCH        (0x0) Controls the type of match generated by this comparator</span></div>
<div class="line"><a id="l00277" name="l00277"></a><span class="lineno">  277</span>    io_rw_32 dwt_function3;</div>
<div class="line"><a id="l00278" name="l00278"></a><span class="lineno">  278</span> </div>
<div class="line"><a id="l00279" name="l00279"></a><span class="lineno">  279</span>    uint32_t _pad18[984];</div>
<div class="line"><a id="l00280" name="l00280"></a><span class="lineno">  280</span> </div>
<div class="line"><a id="l00281" name="l00281"></a><span class="lineno">  281</span>    _REG_(M33_DWT_DEVARCH_OFFSET) <span class="comment">// M33_DWT_DEVARCH</span></div>
<div class="line"><a id="l00282" name="l00282"></a><span class="lineno">  282</span>    <span class="comment">// Provides CoreSight discovery information for the DWT</span></div>
<div class="line"><a id="l00283" name="l00283"></a><span class="lineno">  283</span>    <span class="comment">// 0xffe00000 [31:21] ARCHITECT    (0x23b) Defines the architect of the component</span></div>
<div class="line"><a id="l00284" name="l00284"></a><span class="lineno">  284</span>    <span class="comment">// 0x00100000 [20]    PRESENT      (1) Defines that the DEVARCH register is present</span></div>
<div class="line"><a id="l00285" name="l00285"></a><span class="lineno">  285</span>    <span class="comment">// 0x000f0000 [19:16] REVISION     (0x0) Defines the architecture revision of the component</span></div>
<div class="line"><a id="l00286" name="l00286"></a><span class="lineno">  286</span>    <span class="comment">// 0x0000f000 [15:12] ARCHVER      (0x1) Defines the architecture version of the component</span></div>
<div class="line"><a id="l00287" name="l00287"></a><span class="lineno">  287</span>    <span class="comment">// 0x00000fff [11:0]  ARCHPART     (0xa02) Defines the architecture of the component</span></div>
<div class="line"><a id="l00288" name="l00288"></a><span class="lineno">  288</span>    io_ro_32 dwt_devarch;</div>
<div class="line"><a id="l00289" name="l00289"></a><span class="lineno">  289</span> </div>
<div class="line"><a id="l00290" name="l00290"></a><span class="lineno">  290</span>    uint32_t _pad19[3];</div>
<div class="line"><a id="l00291" name="l00291"></a><span class="lineno">  291</span> </div>
<div class="line"><a id="l00292" name="l00292"></a><span class="lineno">  292</span>    _REG_(M33_DWT_DEVTYPE_OFFSET) <span class="comment">// M33_DWT_DEVTYPE</span></div>
<div class="line"><a id="l00293" name="l00293"></a><span class="lineno">  293</span>    <span class="comment">// Provides CoreSight discovery information for the DWT</span></div>
<div class="line"><a id="l00294" name="l00294"></a><span class="lineno">  294</span>    <span class="comment">// 0x000000f0 [7:4]   SUB          (0x0) Component sub-type</span></div>
<div class="line"><a id="l00295" name="l00295"></a><span class="lineno">  295</span>    <span class="comment">// 0x0000000f [3:0]   MAJOR        (0x0) Component major type</span></div>
<div class="line"><a id="l00296" name="l00296"></a><span class="lineno">  296</span>    io_ro_32 dwt_devtype;</div>
<div class="line"><a id="l00297" name="l00297"></a><span class="lineno">  297</span> </div>
<div class="line"><a id="l00298" name="l00298"></a><span class="lineno">  298</span>    _REG_(M33_DWT_PIDR4_OFFSET) <span class="comment">// M33_DWT_PIDR4</span></div>
<div class="line"><a id="l00299" name="l00299"></a><span class="lineno">  299</span>    <span class="comment">// Provides CoreSight discovery information for the DWT</span></div>
<div class="line"><a id="l00300" name="l00300"></a><span class="lineno">  300</span>    <span class="comment">// 0x000000f0 [7:4]   SIZE         (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00301" name="l00301"></a><span class="lineno">  301</span>    <span class="comment">// 0x0000000f [3:0]   DES_2        (0x4) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00302" name="l00302"></a><span class="lineno">  302</span>    io_ro_32 dwt_pidr4;</div>
<div class="line"><a id="l00303" name="l00303"></a><span class="lineno">  303</span> </div>
<div class="line"><a id="l00304" name="l00304"></a><span class="lineno">  304</span>    _REG_(M33_DWT_PIDR5_OFFSET) <span class="comment">// M33_DWT_PIDR5</span></div>
<div class="line"><a id="l00305" name="l00305"></a><span class="lineno">  305</span>    <span class="comment">// Provides CoreSight discovery information for the DWT</span></div>
<div class="line"><a id="l00306" name="l00306"></a><span class="lineno">  306</span>    <span class="comment">// 0x00000000 [31:0]  DWT_PIDR5    (0x00000000) </span></div>
<div class="line"><a id="l00307" name="l00307"></a><span class="lineno">  307</span>    io_rw_32 dwt_pidr5;</div>
<div class="line"><a id="l00308" name="l00308"></a><span class="lineno">  308</span> </div>
<div class="line"><a id="l00309" name="l00309"></a><span class="lineno">  309</span>    _REG_(M33_DWT_PIDR6_OFFSET) <span class="comment">// M33_DWT_PIDR6</span></div>
<div class="line"><a id="l00310" name="l00310"></a><span class="lineno">  310</span>    <span class="comment">// Provides CoreSight discovery information for the DWT</span></div>
<div class="line"><a id="l00311" name="l00311"></a><span class="lineno">  311</span>    <span class="comment">// 0x00000000 [31:0]  DWT_PIDR6    (0x00000000) </span></div>
<div class="line"><a id="l00312" name="l00312"></a><span class="lineno">  312</span>    io_rw_32 dwt_pidr6;</div>
<div class="line"><a id="l00313" name="l00313"></a><span class="lineno">  313</span> </div>
<div class="line"><a id="l00314" name="l00314"></a><span class="lineno">  314</span>    _REG_(M33_DWT_PIDR7_OFFSET) <span class="comment">// M33_DWT_PIDR7</span></div>
<div class="line"><a id="l00315" name="l00315"></a><span class="lineno">  315</span>    <span class="comment">// Provides CoreSight discovery information for the DWT</span></div>
<div class="line"><a id="l00316" name="l00316"></a><span class="lineno">  316</span>    <span class="comment">// 0x00000000 [31:0]  DWT_PIDR7    (0x00000000) </span></div>
<div class="line"><a id="l00317" name="l00317"></a><span class="lineno">  317</span>    io_rw_32 dwt_pidr7;</div>
<div class="line"><a id="l00318" name="l00318"></a><span class="lineno">  318</span> </div>
<div class="line"><a id="l00319" name="l00319"></a><span class="lineno">  319</span>    _REG_(M33_DWT_PIDR0_OFFSET) <span class="comment">// M33_DWT_PIDR0</span></div>
<div class="line"><a id="l00320" name="l00320"></a><span class="lineno">  320</span>    <span class="comment">// Provides CoreSight discovery information for the DWT</span></div>
<div class="line"><a id="l00321" name="l00321"></a><span class="lineno">  321</span>    <span class="comment">// 0x000000ff [7:0]   PART_0       (0x21) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00322" name="l00322"></a><span class="lineno">  322</span>    io_ro_32 dwt_pidr0;</div>
<div class="line"><a id="l00323" name="l00323"></a><span class="lineno">  323</span> </div>
<div class="line"><a id="l00324" name="l00324"></a><span class="lineno">  324</span>    _REG_(M33_DWT_PIDR1_OFFSET) <span class="comment">// M33_DWT_PIDR1</span></div>
<div class="line"><a id="l00325" name="l00325"></a><span class="lineno">  325</span>    <span class="comment">// Provides CoreSight discovery information for the DWT</span></div>
<div class="line"><a id="l00326" name="l00326"></a><span class="lineno">  326</span>    <span class="comment">// 0x000000f0 [7:4]   DES_0        (0xb) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00327" name="l00327"></a><span class="lineno">  327</span>    <span class="comment">// 0x0000000f [3:0]   PART_1       (0xd) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00328" name="l00328"></a><span class="lineno">  328</span>    io_ro_32 dwt_pidr1;</div>
<div class="line"><a id="l00329" name="l00329"></a><span class="lineno">  329</span> </div>
<div class="line"><a id="l00330" name="l00330"></a><span class="lineno">  330</span>    _REG_(M33_DWT_PIDR2_OFFSET) <span class="comment">// M33_DWT_PIDR2</span></div>
<div class="line"><a id="l00331" name="l00331"></a><span class="lineno">  331</span>    <span class="comment">// Provides CoreSight discovery information for the DWT</span></div>
<div class="line"><a id="l00332" name="l00332"></a><span class="lineno">  332</span>    <span class="comment">// 0x000000f0 [7:4]   REVISION     (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00333" name="l00333"></a><span class="lineno">  333</span>    <span class="comment">// 0x00000008 [3]     JEDEC        (1) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00334" name="l00334"></a><span class="lineno">  334</span>    <span class="comment">// 0x00000007 [2:0]   DES_1        (0x3) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00335" name="l00335"></a><span class="lineno">  335</span>    io_ro_32 dwt_pidr2;</div>
<div class="line"><a id="l00336" name="l00336"></a><span class="lineno">  336</span> </div>
<div class="line"><a id="l00337" name="l00337"></a><span class="lineno">  337</span>    _REG_(M33_DWT_PIDR3_OFFSET) <span class="comment">// M33_DWT_PIDR3</span></div>
<div class="line"><a id="l00338" name="l00338"></a><span class="lineno">  338</span>    <span class="comment">// Provides CoreSight discovery information for the DWT</span></div>
<div class="line"><a id="l00339" name="l00339"></a><span class="lineno">  339</span>    <span class="comment">// 0x000000f0 [7:4]   REVAND       (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00340" name="l00340"></a><span class="lineno">  340</span>    <span class="comment">// 0x0000000f [3:0]   CMOD         (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00341" name="l00341"></a><span class="lineno">  341</span>    io_ro_32 dwt_pidr3;</div>
<div class="line"><a id="l00342" name="l00342"></a><span class="lineno">  342</span> </div>
<div class="line"><a id="l00343" name="l00343"></a><span class="lineno">  343</span>    <span class="comment">// (Description copied from array index 0 register M33_DWT_CIDR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00344" name="l00344"></a><span class="lineno">  344</span>    _REG_(M33_DWT_CIDR0_OFFSET) <span class="comment">// M33_DWT_CIDR0</span></div>
<div class="line"><a id="l00345" name="l00345"></a><span class="lineno">  345</span>    <span class="comment">// Provides CoreSight discovery information for the DWT</span></div>
<div class="line"><a id="l00346" name="l00346"></a><span class="lineno">  346</span>    <span class="comment">// 0x000000ff [7:0]   PRMBL_0      (0x0d) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00347" name="l00347"></a><span class="lineno">  347</span>    io_ro_32 dwt_cidr[4];</div>
<div class="line"><a id="l00348" name="l00348"></a><span class="lineno">  348</span> </div>
<div class="line"><a id="l00349" name="l00349"></a><span class="lineno">  349</span>    _REG_(M33_FP_CTRL_OFFSET) <span class="comment">// M33_FP_CTRL</span></div>
<div class="line"><a id="l00350" name="l00350"></a><span class="lineno">  350</span>    <span class="comment">// Provides FPB implementation information, and the global enable for the FPB unit</span></div>
<div class="line"><a id="l00351" name="l00351"></a><span class="lineno">  351</span>    <span class="comment">// 0xf0000000 [31:28] REV          (0x6) Flash Patch and Breakpoint Unit architecture revision</span></div>
<div class="line"><a id="l00352" name="l00352"></a><span class="lineno">  352</span>    <span class="comment">// 0x00007000 [14:12] NUM_CODE_14_12_ (0x5) Indicates the number of implemented instruction address...</span></div>
<div class="line"><a id="l00353" name="l00353"></a><span class="lineno">  353</span>    <span class="comment">// 0x00000f00 [11:8]  NUM_LIT      (0x5) Indicates the number of implemented literal address comparators</span></div>
<div class="line"><a id="l00354" name="l00354"></a><span class="lineno">  354</span>    <span class="comment">// 0x000000f0 [7:4]   NUM_CODE_7_4_ (0x8) Indicates the number of implemented instruction address...</span></div>
<div class="line"><a id="l00355" name="l00355"></a><span class="lineno">  355</span>    <span class="comment">// 0x00000002 [1]     KEY          (0) Writes to the FP_CTRL are ignored unless KEY is...</span></div>
<div class="line"><a id="l00356" name="l00356"></a><span class="lineno">  356</span>    <span class="comment">// 0x00000001 [0]     ENABLE       (0) Enables the FPB</span></div>
<div class="line"><a id="l00357" name="l00357"></a><span class="lineno">  357</span>    io_rw_32 fp_ctrl;</div>
<div class="line"><a id="l00358" name="l00358"></a><span class="lineno">  358</span> </div>
<div class="line"><a id="l00359" name="l00359"></a><span class="lineno">  359</span>    _REG_(M33_FP_REMAP_OFFSET) <span class="comment">// M33_FP_REMAP</span></div>
<div class="line"><a id="l00360" name="l00360"></a><span class="lineno">  360</span>    <span class="comment">// Indicates whether the implementation supports Flash Patch remap and, if it does, holds the...</span></div>
<div class="line"><a id="l00361" name="l00361"></a><span class="lineno">  361</span>    <span class="comment">// 0x20000000 [29]    RMPSPT       (0) Indicates whether the FPB unit supports the Flash Patch...</span></div>
<div class="line"><a id="l00362" name="l00362"></a><span class="lineno">  362</span>    <span class="comment">// 0x1fffffe0 [28:5]  REMAP        (0x000000) Holds the bits[28:5] of the Flash Patch remap address</span></div>
<div class="line"><a id="l00363" name="l00363"></a><span class="lineno">  363</span>    io_ro_32 fp_remap;</div>
<div class="line"><a id="l00364" name="l00364"></a><span class="lineno">  364</span> </div>
<div class="line"><a id="l00365" name="l00365"></a><span class="lineno">  365</span>    <span class="comment">// (Description copied from array index 0 register M33_FP_COMP0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00366" name="l00366"></a><span class="lineno">  366</span>    _REG_(M33_FP_COMP0_OFFSET) <span class="comment">// M33_FP_COMP0</span></div>
<div class="line"><a id="l00367" name="l00367"></a><span class="lineno">  367</span>    <span class="comment">// Holds an address for comparison</span></div>
<div class="line"><a id="l00368" name="l00368"></a><span class="lineno">  368</span>    <span class="comment">// 0x00000001 [0]     BE           (0) Selects between flashpatch and breakpoint functionality</span></div>
<div class="line"><a id="l00369" name="l00369"></a><span class="lineno">  369</span>    io_rw_32 fp_comp[8];</div>
<div class="line"><a id="l00370" name="l00370"></a><span class="lineno">  370</span> </div>
<div class="line"><a id="l00371" name="l00371"></a><span class="lineno">  371</span>    uint32_t _pad20[997];</div>
<div class="line"><a id="l00372" name="l00372"></a><span class="lineno">  372</span> </div>
<div class="line"><a id="l00373" name="l00373"></a><span class="lineno">  373</span>    _REG_(M33_FP_DEVARCH_OFFSET) <span class="comment">// M33_FP_DEVARCH</span></div>
<div class="line"><a id="l00374" name="l00374"></a><span class="lineno">  374</span>    <span class="comment">// Provides CoreSight discovery information for the FPB</span></div>
<div class="line"><a id="l00375" name="l00375"></a><span class="lineno">  375</span>    <span class="comment">// 0xffe00000 [31:21] ARCHITECT    (0x23b) Defines the architect of the component</span></div>
<div class="line"><a id="l00376" name="l00376"></a><span class="lineno">  376</span>    <span class="comment">// 0x00100000 [20]    PRESENT      (1) Defines that the DEVARCH register is present</span></div>
<div class="line"><a id="l00377" name="l00377"></a><span class="lineno">  377</span>    <span class="comment">// 0x000f0000 [19:16] REVISION     (0x0) Defines the architecture revision of the component</span></div>
<div class="line"><a id="l00378" name="l00378"></a><span class="lineno">  378</span>    <span class="comment">// 0x0000f000 [15:12] ARCHVER      (0x1) Defines the architecture version of the component</span></div>
<div class="line"><a id="l00379" name="l00379"></a><span class="lineno">  379</span>    <span class="comment">// 0x00000fff [11:0]  ARCHPART     (0xa03) Defines the architecture of the component</span></div>
<div class="line"><a id="l00380" name="l00380"></a><span class="lineno">  380</span>    io_ro_32 fp_devarch;</div>
<div class="line"><a id="l00381" name="l00381"></a><span class="lineno">  381</span> </div>
<div class="line"><a id="l00382" name="l00382"></a><span class="lineno">  382</span>    uint32_t _pad21[3];</div>
<div class="line"><a id="l00383" name="l00383"></a><span class="lineno">  383</span> </div>
<div class="line"><a id="l00384" name="l00384"></a><span class="lineno">  384</span>    _REG_(M33_FP_DEVTYPE_OFFSET) <span class="comment">// M33_FP_DEVTYPE</span></div>
<div class="line"><a id="l00385" name="l00385"></a><span class="lineno">  385</span>    <span class="comment">// Provides CoreSight discovery information for the FPB</span></div>
<div class="line"><a id="l00386" name="l00386"></a><span class="lineno">  386</span>    <span class="comment">// 0x000000f0 [7:4]   SUB          (0x0) Component sub-type</span></div>
<div class="line"><a id="l00387" name="l00387"></a><span class="lineno">  387</span>    <span class="comment">// 0x0000000f [3:0]   MAJOR        (0x0) Component major type</span></div>
<div class="line"><a id="l00388" name="l00388"></a><span class="lineno">  388</span>    io_ro_32 fp_devtype;</div>
<div class="line"><a id="l00389" name="l00389"></a><span class="lineno">  389</span> </div>
<div class="line"><a id="l00390" name="l00390"></a><span class="lineno">  390</span>    _REG_(M33_FP_PIDR4_OFFSET) <span class="comment">// M33_FP_PIDR4</span></div>
<div class="line"><a id="l00391" name="l00391"></a><span class="lineno">  391</span>    <span class="comment">// Provides CoreSight discovery information for the FP</span></div>
<div class="line"><a id="l00392" name="l00392"></a><span class="lineno">  392</span>    <span class="comment">// 0x000000f0 [7:4]   SIZE         (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00393" name="l00393"></a><span class="lineno">  393</span>    <span class="comment">// 0x0000000f [3:0]   DES_2        (0x4) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00394" name="l00394"></a><span class="lineno">  394</span>    io_ro_32 fp_pidr4;</div>
<div class="line"><a id="l00395" name="l00395"></a><span class="lineno">  395</span> </div>
<div class="line"><a id="l00396" name="l00396"></a><span class="lineno">  396</span>    _REG_(M33_FP_PIDR5_OFFSET) <span class="comment">// M33_FP_PIDR5</span></div>
<div class="line"><a id="l00397" name="l00397"></a><span class="lineno">  397</span>    <span class="comment">// Provides CoreSight discovery information for the FP</span></div>
<div class="line"><a id="l00398" name="l00398"></a><span class="lineno">  398</span>    <span class="comment">// 0x00000000 [31:0]  FP_PIDR5     (0x00000000) </span></div>
<div class="line"><a id="l00399" name="l00399"></a><span class="lineno">  399</span>    io_rw_32 fp_pidr5;</div>
<div class="line"><a id="l00400" name="l00400"></a><span class="lineno">  400</span> </div>
<div class="line"><a id="l00401" name="l00401"></a><span class="lineno">  401</span>    _REG_(M33_FP_PIDR6_OFFSET) <span class="comment">// M33_FP_PIDR6</span></div>
<div class="line"><a id="l00402" name="l00402"></a><span class="lineno">  402</span>    <span class="comment">// Provides CoreSight discovery information for the FP</span></div>
<div class="line"><a id="l00403" name="l00403"></a><span class="lineno">  403</span>    <span class="comment">// 0x00000000 [31:0]  FP_PIDR6     (0x00000000) </span></div>
<div class="line"><a id="l00404" name="l00404"></a><span class="lineno">  404</span>    io_rw_32 fp_pidr6;</div>
<div class="line"><a id="l00405" name="l00405"></a><span class="lineno">  405</span> </div>
<div class="line"><a id="l00406" name="l00406"></a><span class="lineno">  406</span>    _REG_(M33_FP_PIDR7_OFFSET) <span class="comment">// M33_FP_PIDR7</span></div>
<div class="line"><a id="l00407" name="l00407"></a><span class="lineno">  407</span>    <span class="comment">// Provides CoreSight discovery information for the FP</span></div>
<div class="line"><a id="l00408" name="l00408"></a><span class="lineno">  408</span>    <span class="comment">// 0x00000000 [31:0]  FP_PIDR7     (0x00000000) </span></div>
<div class="line"><a id="l00409" name="l00409"></a><span class="lineno">  409</span>    io_rw_32 fp_pidr7;</div>
<div class="line"><a id="l00410" name="l00410"></a><span class="lineno">  410</span> </div>
<div class="line"><a id="l00411" name="l00411"></a><span class="lineno">  411</span>    _REG_(M33_FP_PIDR0_OFFSET) <span class="comment">// M33_FP_PIDR0</span></div>
<div class="line"><a id="l00412" name="l00412"></a><span class="lineno">  412</span>    <span class="comment">// Provides CoreSight discovery information for the FP</span></div>
<div class="line"><a id="l00413" name="l00413"></a><span class="lineno">  413</span>    <span class="comment">// 0x000000ff [7:0]   PART_0       (0x21) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00414" name="l00414"></a><span class="lineno">  414</span>    io_ro_32 fp_pidr0;</div>
<div class="line"><a id="l00415" name="l00415"></a><span class="lineno">  415</span> </div>
<div class="line"><a id="l00416" name="l00416"></a><span class="lineno">  416</span>    _REG_(M33_FP_PIDR1_OFFSET) <span class="comment">// M33_FP_PIDR1</span></div>
<div class="line"><a id="l00417" name="l00417"></a><span class="lineno">  417</span>    <span class="comment">// Provides CoreSight discovery information for the FP</span></div>
<div class="line"><a id="l00418" name="l00418"></a><span class="lineno">  418</span>    <span class="comment">// 0x000000f0 [7:4]   DES_0        (0xb) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00419" name="l00419"></a><span class="lineno">  419</span>    <span class="comment">// 0x0000000f [3:0]   PART_1       (0xd) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00420" name="l00420"></a><span class="lineno">  420</span>    io_ro_32 fp_pidr1;</div>
<div class="line"><a id="l00421" name="l00421"></a><span class="lineno">  421</span> </div>
<div class="line"><a id="l00422" name="l00422"></a><span class="lineno">  422</span>    _REG_(M33_FP_PIDR2_OFFSET) <span class="comment">// M33_FP_PIDR2</span></div>
<div class="line"><a id="l00423" name="l00423"></a><span class="lineno">  423</span>    <span class="comment">// Provides CoreSight discovery information for the FP</span></div>
<div class="line"><a id="l00424" name="l00424"></a><span class="lineno">  424</span>    <span class="comment">// 0x000000f0 [7:4]   REVISION     (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00425" name="l00425"></a><span class="lineno">  425</span>    <span class="comment">// 0x00000008 [3]     JEDEC        (1) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00426" name="l00426"></a><span class="lineno">  426</span>    <span class="comment">// 0x00000007 [2:0]   DES_1        (0x3) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00427" name="l00427"></a><span class="lineno">  427</span>    io_ro_32 fp_pidr2;</div>
<div class="line"><a id="l00428" name="l00428"></a><span class="lineno">  428</span> </div>
<div class="line"><a id="l00429" name="l00429"></a><span class="lineno">  429</span>    _REG_(M33_FP_PIDR3_OFFSET) <span class="comment">// M33_FP_PIDR3</span></div>
<div class="line"><a id="l00430" name="l00430"></a><span class="lineno">  430</span>    <span class="comment">// Provides CoreSight discovery information for the FP</span></div>
<div class="line"><a id="l00431" name="l00431"></a><span class="lineno">  431</span>    <span class="comment">// 0x000000f0 [7:4]   REVAND       (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00432" name="l00432"></a><span class="lineno">  432</span>    <span class="comment">// 0x0000000f [3:0]   CMOD         (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00433" name="l00433"></a><span class="lineno">  433</span>    io_ro_32 fp_pidr3;</div>
<div class="line"><a id="l00434" name="l00434"></a><span class="lineno">  434</span> </div>
<div class="line"><a id="l00435" name="l00435"></a><span class="lineno">  435</span>    <span class="comment">// (Description copied from array index 0 register M33_FP_CIDR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00436" name="l00436"></a><span class="lineno">  436</span>    _REG_(M33_FP_CIDR0_OFFSET) <span class="comment">// M33_FP_CIDR0</span></div>
<div class="line"><a id="l00437" name="l00437"></a><span class="lineno">  437</span>    <span class="comment">// Provides CoreSight discovery information for the FP</span></div>
<div class="line"><a id="l00438" name="l00438"></a><span class="lineno">  438</span>    <span class="comment">// 0x000000ff [7:0]   PRMBL_0      (0x0d) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l00439" name="l00439"></a><span class="lineno">  439</span>    io_ro_32 fp_cidr[4];</div>
<div class="line"><a id="l00440" name="l00440"></a><span class="lineno">  440</span> </div>
<div class="line"><a id="l00441" name="l00441"></a><span class="lineno">  441</span>    uint32_t _pad22[11265];</div>
<div class="line"><a id="l00442" name="l00442"></a><span class="lineno">  442</span> </div>
<div class="line"><a id="l00443" name="l00443"></a><span class="lineno">  443</span>    _REG_(M33_ICTR_OFFSET) <span class="comment">// M33_ICTR</span></div>
<div class="line"><a id="l00444" name="l00444"></a><span class="lineno">  444</span>    <span class="comment">// Provides information about the interrupt controller</span></div>
<div class="line"><a id="l00445" name="l00445"></a><span class="lineno">  445</span>    <span class="comment">// 0x0000000f [3:0]   INTLINESNUM  (0x1) Indicates the number of the highest implemented register...</span></div>
<div class="line"><a id="l00446" name="l00446"></a><span class="lineno">  446</span>    io_ro_32 ictr;</div>
<div class="line"><a id="l00447" name="l00447"></a><span class="lineno">  447</span> </div>
<div class="line"><a id="l00448" name="l00448"></a><span class="lineno">  448</span>    _REG_(M33_ACTLR_OFFSET) <span class="comment">// M33_ACTLR</span></div>
<div class="line"><a id="l00449" name="l00449"></a><span class="lineno">  449</span>    <span class="comment">// Provides IMPLEMENTATION DEFINED configuration and control options</span></div>
<div class="line"><a id="l00450" name="l00450"></a><span class="lineno">  450</span>    <span class="comment">// 0x20000000 [29]    EXTEXCLALL   (0) External Exclusives Allowed with no MPU</span></div>
<div class="line"><a id="l00451" name="l00451"></a><span class="lineno">  451</span>    <span class="comment">// 0x00001000 [12]    DISITMATBFLUSH (0) Disable ATB Flush</span></div>
<div class="line"><a id="l00452" name="l00452"></a><span class="lineno">  452</span>    <span class="comment">// 0x00000400 [10]    FPEXCODIS    (0) Disable FPU exception outputs</span></div>
<div class="line"><a id="l00453" name="l00453"></a><span class="lineno">  453</span>    <span class="comment">// 0x00000200 [9]     DISOOFP      (0) Disable out-of-order FP instruction completion</span></div>
<div class="line"><a id="l00454" name="l00454"></a><span class="lineno">  454</span>    <span class="comment">// 0x00000004 [2]     DISFOLD      (0) Disable dual-issue</span></div>
<div class="line"><a id="l00455" name="l00455"></a><span class="lineno">  455</span>    <span class="comment">// 0x00000001 [0]     DISMCYCINT   (0) Disable dual-issue</span></div>
<div class="line"><a id="l00456" name="l00456"></a><span class="lineno">  456</span>    io_rw_32 actlr;</div>
<div class="line"><a id="l00457" name="l00457"></a><span class="lineno">  457</span> </div>
<div class="line"><a id="l00458" name="l00458"></a><span class="lineno">  458</span>    uint32_t _pad23;</div>
<div class="line"><a id="l00459" name="l00459"></a><span class="lineno">  459</span> </div>
<div class="line"><a id="l00460" name="l00460"></a><span class="lineno">  460</span>    _REG_(M33_SYST_CSR_OFFSET) <span class="comment">// M33_SYST_CSR</span></div>
<div class="line"><a id="l00461" name="l00461"></a><span class="lineno">  461</span>    <span class="comment">// SysTick Control and Status Register</span></div>
<div class="line"><a id="l00462" name="l00462"></a><span class="lineno">  462</span>    <span class="comment">// 0x00010000 [16]    COUNTFLAG    (0) Returns 1 if timer counted to 0 since last time this was read</span></div>
<div class="line"><a id="l00463" name="l00463"></a><span class="lineno">  463</span>    <span class="comment">// 0x00000004 [2]     CLKSOURCE    (0) SysTick clock source</span></div>
<div class="line"><a id="l00464" name="l00464"></a><span class="lineno">  464</span>    <span class="comment">// 0x00000002 [1]     TICKINT      (0) Enables SysTick exception request: +</span></div>
<div class="line"><a id="l00465" name="l00465"></a><span class="lineno">  465</span>    <span class="comment">// 0x00000001 [0]     ENABLE       (0) Enable SysTick counter: +</span></div>
<div class="line"><a id="l00466" name="l00466"></a><span class="lineno">  466</span>    io_rw_32 syst_csr;</div>
<div class="line"><a id="l00467" name="l00467"></a><span class="lineno">  467</span> </div>
<div class="line"><a id="l00468" name="l00468"></a><span class="lineno">  468</span>    _REG_(M33_SYST_RVR_OFFSET) <span class="comment">// M33_SYST_RVR</span></div>
<div class="line"><a id="l00469" name="l00469"></a><span class="lineno">  469</span>    <span class="comment">// SysTick Reload Value Register</span></div>
<div class="line"><a id="l00470" name="l00470"></a><span class="lineno">  470</span>    <span class="comment">// 0x00ffffff [23:0]  RELOAD       (0x000000) Value to load into the SysTick Current Value Register...</span></div>
<div class="line"><a id="l00471" name="l00471"></a><span class="lineno">  471</span>    io_rw_32 syst_rvr;</div>
<div class="line"><a id="l00472" name="l00472"></a><span class="lineno">  472</span> </div>
<div class="line"><a id="l00473" name="l00473"></a><span class="lineno">  473</span>    _REG_(M33_SYST_CVR_OFFSET) <span class="comment">// M33_SYST_CVR</span></div>
<div class="line"><a id="l00474" name="l00474"></a><span class="lineno">  474</span>    <span class="comment">// SysTick Current Value Register</span></div>
<div class="line"><a id="l00475" name="l00475"></a><span class="lineno">  475</span>    <span class="comment">// 0x00ffffff [23:0]  CURRENT      (0x000000) Reads return the current value of the SysTick counter</span></div>
<div class="line"><a id="l00476" name="l00476"></a><span class="lineno">  476</span>    io_rw_32 syst_cvr;</div>
<div class="line"><a id="l00477" name="l00477"></a><span class="lineno">  477</span> </div>
<div class="line"><a id="l00478" name="l00478"></a><span class="lineno">  478</span>    _REG_(M33_SYST_CALIB_OFFSET) <span class="comment">// M33_SYST_CALIB</span></div>
<div class="line"><a id="l00479" name="l00479"></a><span class="lineno">  479</span>    <span class="comment">// SysTick Calibration Value Register</span></div>
<div class="line"><a id="l00480" name="l00480"></a><span class="lineno">  480</span>    <span class="comment">// 0x80000000 [31]    NOREF        (0) If reads as 1, the Reference clock is not provided - the...</span></div>
<div class="line"><a id="l00481" name="l00481"></a><span class="lineno">  481</span>    <span class="comment">// 0x40000000 [30]    SKEW         (0) If reads as 1, the calibration value for 10ms is inexact...</span></div>
<div class="line"><a id="l00482" name="l00482"></a><span class="lineno">  482</span>    <span class="comment">// 0x00ffffff [23:0]  TENMS        (0x000000) An optional Reload value to be used for 10ms (100Hz)...</span></div>
<div class="line"><a id="l00483" name="l00483"></a><span class="lineno">  483</span>    io_ro_32 syst_calib;</div>
<div class="line"><a id="l00484" name="l00484"></a><span class="lineno">  484</span> </div>
<div class="line"><a id="l00485" name="l00485"></a><span class="lineno">  485</span>    uint32_t _pad24[56];</div>
<div class="line"><a id="l00486" name="l00486"></a><span class="lineno">  486</span> </div>
<div class="line"><a id="l00487" name="l00487"></a><span class="lineno">  487</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00488" name="l00488"></a><span class="lineno">  488</span>    _REG_(M33_NVIC_ISER0_OFFSET) <span class="comment">// M33_NVIC_ISER0</span></div>
<div class="line"><a id="l00489" name="l00489"></a><span class="lineno">  489</span>    <span class="comment">// Enables or reads the enabled state of each group of 32 interrupts</span></div>
<div class="line"><a id="l00490" name="l00490"></a><span class="lineno">  490</span>    <span class="comment">// 0xffffffff [31:0]  SETENA       (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether...</span></div>
<div class="line"><a id="l00491" name="l00491"></a><span class="lineno">  491</span>    io_rw_32 nvic_iser[2];</div>
<div class="line"><a id="l00492" name="l00492"></a><span class="lineno">  492</span> </div>
<div class="line"><a id="l00493" name="l00493"></a><span class="lineno">  493</span>    uint32_t _pad25[30];</div>
<div class="line"><a id="l00494" name="l00494"></a><span class="lineno">  494</span> </div>
<div class="line"><a id="l00495" name="l00495"></a><span class="lineno">  495</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00496" name="l00496"></a><span class="lineno">  496</span>    _REG_(M33_NVIC_ICER0_OFFSET) <span class="comment">// M33_NVIC_ICER0</span></div>
<div class="line"><a id="l00497" name="l00497"></a><span class="lineno">  497</span>    <span class="comment">// Clears or reads the enabled state of each group of 32 interrupts</span></div>
<div class="line"><a id="l00498" name="l00498"></a><span class="lineno">  498</span>    <span class="comment">// 0xffffffff [31:0]  CLRENA       (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether...</span></div>
<div class="line"><a id="l00499" name="l00499"></a><span class="lineno">  499</span>    io_rw_32 nvic_icer[2];</div>
<div class="line"><a id="l00500" name="l00500"></a><span class="lineno">  500</span> </div>
<div class="line"><a id="l00501" name="l00501"></a><span class="lineno">  501</span>    uint32_t _pad26[30];</div>
<div class="line"><a id="l00502" name="l00502"></a><span class="lineno">  502</span> </div>
<div class="line"><a id="l00503" name="l00503"></a><span class="lineno">  503</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00504" name="l00504"></a><span class="lineno">  504</span>    _REG_(M33_NVIC_ISPR0_OFFSET) <span class="comment">// M33_NVIC_ISPR0</span></div>
<div class="line"><a id="l00505" name="l00505"></a><span class="lineno">  505</span>    <span class="comment">// Enables or reads the pending state of each group of 32 interrupts</span></div>
<div class="line"><a id="l00506" name="l00506"></a><span class="lineno">  506</span>    <span class="comment">// 0xffffffff [31:0]  SETPEND      (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether...</span></div>
<div class="line"><a id="l00507" name="l00507"></a><span class="lineno">  507</span>    io_rw_32 nvic_ispr[2];</div>
<div class="line"><a id="l00508" name="l00508"></a><span class="lineno">  508</span> </div>
<div class="line"><a id="l00509" name="l00509"></a><span class="lineno">  509</span>    uint32_t _pad27[30];</div>
<div class="line"><a id="l00510" name="l00510"></a><span class="lineno">  510</span> </div>
<div class="line"><a id="l00511" name="l00511"></a><span class="lineno">  511</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00512" name="l00512"></a><span class="lineno">  512</span>    _REG_(M33_NVIC_ICPR0_OFFSET) <span class="comment">// M33_NVIC_ICPR0</span></div>
<div class="line"><a id="l00513" name="l00513"></a><span class="lineno">  513</span>    <span class="comment">// Clears or reads the pending state of each group of 32 interrupts</span></div>
<div class="line"><a id="l00514" name="l00514"></a><span class="lineno">  514</span>    <span class="comment">// 0xffffffff [31:0]  CLRPEND      (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether...</span></div>
<div class="line"><a id="l00515" name="l00515"></a><span class="lineno">  515</span>    io_rw_32 nvic_icpr[2];</div>
<div class="line"><a id="l00516" name="l00516"></a><span class="lineno">  516</span> </div>
<div class="line"><a id="l00517" name="l00517"></a><span class="lineno">  517</span>    uint32_t _pad28[30];</div>
<div class="line"><a id="l00518" name="l00518"></a><span class="lineno">  518</span> </div>
<div class="line"><a id="l00519" name="l00519"></a><span class="lineno">  519</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00520" name="l00520"></a><span class="lineno">  520</span>    _REG_(M33_NVIC_IABR0_OFFSET) <span class="comment">// M33_NVIC_IABR0</span></div>
<div class="line"><a id="l00521" name="l00521"></a><span class="lineno">  521</span>    <span class="comment">// For each group of 32 interrupts, shows the active state of each interrupt</span></div>
<div class="line"><a id="l00522" name="l00522"></a><span class="lineno">  522</span>    <span class="comment">// 0xffffffff [31:0]  ACTIVE       (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state...</span></div>
<div class="line"><a id="l00523" name="l00523"></a><span class="lineno">  523</span>    io_rw_32 nvic_iabr[2];</div>
<div class="line"><a id="l00524" name="l00524"></a><span class="lineno">  524</span> </div>
<div class="line"><a id="l00525" name="l00525"></a><span class="lineno">  525</span>    uint32_t _pad29[30];</div>
<div class="line"><a id="l00526" name="l00526"></a><span class="lineno">  526</span> </div>
<div class="line"><a id="l00527" name="l00527"></a><span class="lineno">  527</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00528" name="l00528"></a><span class="lineno">  528</span>    _REG_(M33_NVIC_ITNS0_OFFSET) <span class="comment">// M33_NVIC_ITNS0</span></div>
<div class="line"><a id="l00529" name="l00529"></a><span class="lineno">  529</span>    <span class="comment">// For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state</span></div>
<div class="line"><a id="l00530" name="l00530"></a><span class="lineno">  530</span>    <span class="comment">// 0xffffffff [31:0]  ITNS         (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security...</span></div>
<div class="line"><a id="l00531" name="l00531"></a><span class="lineno">  531</span>    io_rw_32 nvic_itns[2];</div>
<div class="line"><a id="l00532" name="l00532"></a><span class="lineno">  532</span> </div>
<div class="line"><a id="l00533" name="l00533"></a><span class="lineno">  533</span>    uint32_t _pad30[30];</div>
<div class="line"><a id="l00534" name="l00534"></a><span class="lineno">  534</span> </div>
<div class="line"><a id="l00535" name="l00535"></a><span class="lineno">  535</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00536" name="l00536"></a><span class="lineno">  536</span>    _REG_(M33_NVIC_IPR0_OFFSET) <span class="comment">// M33_NVIC_IPR0</span></div>
<div class="line"><a id="l00537" name="l00537"></a><span class="lineno">  537</span>    <span class="comment">// Sets or reads interrupt priorities</span></div>
<div class="line"><a id="l00538" name="l00538"></a><span class="lineno">  538</span>    <span class="comment">// 0xf0000000 [31:28] PRI_N3       (0x0) For register NVIC_IPRn, the priority of interrupt number...</span></div>
<div class="line"><a id="l00539" name="l00539"></a><span class="lineno">  539</span>    <span class="comment">// 0x00f00000 [23:20] PRI_N2       (0x0) For register NVIC_IPRn, the priority of interrupt number...</span></div>
<div class="line"><a id="l00540" name="l00540"></a><span class="lineno">  540</span>    <span class="comment">// 0x0000f000 [15:12] PRI_N1       (0x0) For register NVIC_IPRn, the priority of interrupt number...</span></div>
<div class="line"><a id="l00541" name="l00541"></a><span class="lineno">  541</span>    <span class="comment">// 0x000000f0 [7:4]   PRI_N0       (0x0) For register NVIC_IPRn, the priority of interrupt number...</span></div>
<div class="line"><a id="l00542" name="l00542"></a><span class="lineno">  542</span>    io_rw_32 nvic_ipr[16];</div>
<div class="line"><a id="l00543" name="l00543"></a><span class="lineno">  543</span> </div>
<div class="line"><a id="l00544" name="l00544"></a><span class="lineno">  544</span>    uint32_t _pad31[560];</div>
<div class="line"><a id="l00545" name="l00545"></a><span class="lineno">  545</span> </div>
<div class="line"><a id="l00546" name="l00546"></a><span class="lineno">  546</span>    _REG_(M33_CPUID_OFFSET) <span class="comment">// M33_CPUID</span></div>
<div class="line"><a id="l00547" name="l00547"></a><span class="lineno">  547</span>    <span class="comment">// Provides identification information for the PE, including an implementer code for the device and...</span></div>
<div class="line"><a id="l00548" name="l00548"></a><span class="lineno">  548</span>    <span class="comment">// 0xff000000 [31:24] IMPLEMENTER  (0x41) This field must hold an implementer code that has been...</span></div>
<div class="line"><a id="l00549" name="l00549"></a><span class="lineno">  549</span>    <span class="comment">// 0x00f00000 [23:20] VARIANT      (0x1) IMPLEMENTATION DEFINED variant number</span></div>
<div class="line"><a id="l00550" name="l00550"></a><span class="lineno">  550</span>    <span class="comment">// 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE</span></div>
<div class="line"><a id="l00551" name="l00551"></a><span class="lineno">  551</span>    <span class="comment">// 0x0000fff0 [15:4]  PARTNO       (0xd21) IMPLEMENTATION DEFINED primary part number for the device</span></div>
<div class="line"><a id="l00552" name="l00552"></a><span class="lineno">  552</span>    <span class="comment">// 0x0000000f [3:0]   REVISION     (0x0) IMPLEMENTATION DEFINED revision number for the device</span></div>
<div class="line"><a id="l00553" name="l00553"></a><span class="lineno">  553</span>    io_ro_32 cpuid;</div>
<div class="line"><a id="l00554" name="l00554"></a><span class="lineno">  554</span> </div>
<div class="line"><a id="l00555" name="l00555"></a><span class="lineno">  555</span>    _REG_(M33_ICSR_OFFSET) <span class="comment">// M33_ICSR</span></div>
<div class="line"><a id="l00556" name="l00556"></a><span class="lineno">  556</span>    <span class="comment">// Controls and provides status information for NMI, PendSV, SysTick and interrupts</span></div>
<div class="line"><a id="l00557" name="l00557"></a><span class="lineno">  557</span>    <span class="comment">// 0x80000000 [31]    PENDNMISET   (0) Indicates whether the NMI exception is pending</span></div>
<div class="line"><a id="l00558" name="l00558"></a><span class="lineno">  558</span>    <span class="comment">// 0x40000000 [30]    PENDNMICLR   (0) Allows the NMI exception pend state to be cleared</span></div>
<div class="line"><a id="l00559" name="l00559"></a><span class="lineno">  559</span>    <span class="comment">// 0x10000000 [28]    PENDSVSET    (0) Indicates whether the PendSV `FTSSS exception is pending</span></div>
<div class="line"><a id="l00560" name="l00560"></a><span class="lineno">  560</span>    <span class="comment">// 0x08000000 [27]    PENDSVCLR    (0) Allows the PendSV exception pend state to be cleared `FTSSS</span></div>
<div class="line"><a id="l00561" name="l00561"></a><span class="lineno">  561</span>    <span class="comment">// 0x04000000 [26]    PENDSTSET    (0) Indicates whether the SysTick `FTSSS exception is pending</span></div>
<div class="line"><a id="l00562" name="l00562"></a><span class="lineno">  562</span>    <span class="comment">// 0x02000000 [25]    PENDSTCLR    (0) Allows the SysTick exception pend state to be cleared `FTSSS</span></div>
<div class="line"><a id="l00563" name="l00563"></a><span class="lineno">  563</span>    <span class="comment">// 0x01000000 [24]    STTNS        (0) Controls whether in a single SysTick implementation, the...</span></div>
<div class="line"><a id="l00564" name="l00564"></a><span class="lineno">  564</span>    <span class="comment">// 0x00800000 [23]    ISRPREEMPT   (0) Indicates whether a pending exception will be serviced...</span></div>
<div class="line"><a id="l00565" name="l00565"></a><span class="lineno">  565</span>    <span class="comment">// 0x00400000 [22]    ISRPENDING   (0) Indicates whether an external interrupt, generated by...</span></div>
<div class="line"><a id="l00566" name="l00566"></a><span class="lineno">  566</span>    <span class="comment">// 0x001ff000 [20:12] VECTPENDING  (0x000) The exception number of the highest priority pending and...</span></div>
<div class="line"><a id="l00567" name="l00567"></a><span class="lineno">  567</span>    <span class="comment">// 0x00000800 [11]    RETTOBASE    (0) In Handler mode, indicates whether there is more than...</span></div>
<div class="line"><a id="l00568" name="l00568"></a><span class="lineno">  568</span>    <span class="comment">// 0x000001ff [8:0]   VECTACTIVE   (0x000) The exception number of the current executing exception</span></div>
<div class="line"><a id="l00569" name="l00569"></a><span class="lineno">  569</span>    io_rw_32 icsr;</div>
<div class="line"><a id="l00570" name="l00570"></a><span class="lineno">  570</span> </div>
<div class="line"><a id="l00571" name="l00571"></a><span class="lineno">  571</span>    _REG_(M33_VTOR_OFFSET) <span class="comment">// M33_VTOR</span></div>
<div class="line"><a id="l00572" name="l00572"></a><span class="lineno">  572</span>    <span class="comment">// Vector Table Offset Register</span></div>
<div class="line"><a id="l00573" name="l00573"></a><span class="lineno">  573</span>    <span class="comment">// 0xffffff80 [31:7]  TBLOFF       (0x0000000) Vector table base offset field</span></div>
<div class="line"><a id="l00574" name="l00574"></a><span class="lineno">  574</span>    io_rw_32 vtor;</div>
<div class="line"><a id="l00575" name="l00575"></a><span class="lineno">  575</span> </div>
<div class="line"><a id="l00576" name="l00576"></a><span class="lineno">  576</span>    _REG_(M33_AIRCR_OFFSET) <span class="comment">// M33_AIRCR</span></div>
<div class="line"><a id="l00577" name="l00577"></a><span class="lineno">  577</span>    <span class="comment">// Application Interrupt and Reset Control Register</span></div>
<div class="line"><a id="l00578" name="l00578"></a><span class="lineno">  578</span>    <span class="comment">// 0xffff0000 [31:16] VECTKEY      (0x0000) Register key: +</span></div>
<div class="line"><a id="l00579" name="l00579"></a><span class="lineno">  579</span>    <span class="comment">// 0x00008000 [15]    ENDIANESS    (0) Data endianness implemented: +</span></div>
<div class="line"><a id="l00580" name="l00580"></a><span class="lineno">  580</span>    <span class="comment">// 0x00004000 [14]    PRIS         (0) Prioritize Secure exceptions</span></div>
<div class="line"><a id="l00581" name="l00581"></a><span class="lineno">  581</span>    <span class="comment">// 0x00002000 [13]    BFHFNMINS    (0) BusFault, HardFault, and NMI Non-secure enable</span></div>
<div class="line"><a id="l00582" name="l00582"></a><span class="lineno">  582</span>    <span class="comment">// 0x00000700 [10:8]  PRIGROUP     (0x0) Interrupt priority grouping field</span></div>
<div class="line"><a id="l00583" name="l00583"></a><span class="lineno">  583</span>    <span class="comment">// 0x00000008 [3]     SYSRESETREQS (0) System reset request, Secure state only</span></div>
<div class="line"><a id="l00584" name="l00584"></a><span class="lineno">  584</span>    <span class="comment">// 0x00000004 [2]     SYSRESETREQ  (0) Writing 1 to this bit causes the SYSRESETREQ signal to...</span></div>
<div class="line"><a id="l00585" name="l00585"></a><span class="lineno">  585</span>    <span class="comment">// 0x00000002 [1]     VECTCLRACTIVE (0) Clears all active state information for fixed and...</span></div>
<div class="line"><a id="l00586" name="l00586"></a><span class="lineno">  586</span>    io_rw_32 aircr;</div>
<div class="line"><a id="l00587" name="l00587"></a><span class="lineno">  587</span> </div>
<div class="line"><a id="l00588" name="l00588"></a><span class="lineno">  588</span>    _REG_(M33_SCR_OFFSET) <span class="comment">// M33_SCR</span></div>
<div class="line"><a id="l00589" name="l00589"></a><span class="lineno">  589</span>    <span class="comment">// System Control Register</span></div>
<div class="line"><a id="l00590" name="l00590"></a><span class="lineno">  590</span>    <span class="comment">// 0x00000010 [4]     SEVONPEND    (0) Send Event on Pending bit: +</span></div>
<div class="line"><a id="l00591" name="l00591"></a><span class="lineno">  591</span>    <span class="comment">// 0x00000008 [3]     SLEEPDEEPS   (0) 0 SLEEPDEEP is available to both security states +</span></div>
<div class="line"><a id="l00592" name="l00592"></a><span class="lineno">  592</span>    <span class="comment">// 0x00000004 [2]     SLEEPDEEP    (0) Controls whether the processor uses sleep or deep sleep...</span></div>
<div class="line"><a id="l00593" name="l00593"></a><span class="lineno">  593</span>    <span class="comment">// 0x00000002 [1]     SLEEPONEXIT  (0) Indicates sleep-on-exit when returning from Handler mode...</span></div>
<div class="line"><a id="l00594" name="l00594"></a><span class="lineno">  594</span>    io_rw_32 scr;</div>
<div class="line"><a id="l00595" name="l00595"></a><span class="lineno">  595</span> </div>
<div class="line"><a id="l00596" name="l00596"></a><span class="lineno">  596</span>    _REG_(M33_CCR_OFFSET) <span class="comment">// M33_CCR</span></div>
<div class="line"><a id="l00597" name="l00597"></a><span class="lineno">  597</span>    <span class="comment">// Sets or returns configuration and control data</span></div>
<div class="line"><a id="l00598" name="l00598"></a><span class="lineno">  598</span>    <span class="comment">// 0x00040000 [18]    BP           (0) Enables program flow prediction `FTSSS</span></div>
<div class="line"><a id="l00599" name="l00599"></a><span class="lineno">  599</span>    <span class="comment">// 0x00020000 [17]    IC           (0) This is a global enable bit for instruction caches in...</span></div>
<div class="line"><a id="l00600" name="l00600"></a><span class="lineno">  600</span>    <span class="comment">// 0x00010000 [16]    DC           (0) Enables data caching of all data accesses to Normal memory `FTSSS</span></div>
<div class="line"><a id="l00601" name="l00601"></a><span class="lineno">  601</span>    <span class="comment">// 0x00000400 [10]    STKOFHFNMIGN (0) Controls the effect of a stack limit violation while...</span></div>
<div class="line"><a id="l00602" name="l00602"></a><span class="lineno">  602</span>    <span class="comment">// 0x00000200 [9]     RES1         (1) Reserved, RES1</span></div>
<div class="line"><a id="l00603" name="l00603"></a><span class="lineno">  603</span>    <span class="comment">// 0x00000100 [8]     BFHFNMIGN    (0) Determines the effect of precise BusFaults on handlers...</span></div>
<div class="line"><a id="l00604" name="l00604"></a><span class="lineno">  604</span>    <span class="comment">// 0x00000010 [4]     DIV_0_TRP    (0) Controls the generation of a DIVBYZERO UsageFault when...</span></div>
<div class="line"><a id="l00605" name="l00605"></a><span class="lineno">  605</span>    <span class="comment">// 0x00000008 [3]     UNALIGN_TRP  (0) Controls the trapping of unaligned word or halfword accesses</span></div>
<div class="line"><a id="l00606" name="l00606"></a><span class="lineno">  606</span>    <span class="comment">// 0x00000002 [1]     USERSETMPEND (0) Determines whether unprivileged accesses are permitted...</span></div>
<div class="line"><a id="l00607" name="l00607"></a><span class="lineno">  607</span>    <span class="comment">// 0x00000001 [0]     RES1_1       (1) Reserved, RES1</span></div>
<div class="line"><a id="l00608" name="l00608"></a><span class="lineno">  608</span>    io_rw_32 ccr;</div>
<div class="line"><a id="l00609" name="l00609"></a><span class="lineno">  609</span> </div>
<div class="line"><a id="l00610" name="l00610"></a><span class="lineno">  610</span>    <span class="comment">// (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00611" name="l00611"></a><span class="lineno">  611</span>    _REG_(M33_SHPR1_OFFSET) <span class="comment">// M33_SHPR1</span></div>
<div class="line"><a id="l00612" name="l00612"></a><span class="lineno">  612</span>    <span class="comment">// Sets or returns priority for system handlers 4 - 7</span></div>
<div class="line"><a id="l00613" name="l00613"></a><span class="lineno">  613</span>    <span class="comment">// 0xe0000000 [31:29] PRI_7_3      (0x0) Priority of system handler 7, SecureFault</span></div>
<div class="line"><a id="l00614" name="l00614"></a><span class="lineno">  614</span>    <span class="comment">// 0x00e00000 [23:21] PRI_6_3      (0x0) Priority of system handler 6, SecureFault</span></div>
<div class="line"><a id="l00615" name="l00615"></a><span class="lineno">  615</span>    <span class="comment">// 0x0000e000 [15:13] PRI_5_3      (0x0) Priority of system handler 5, SecureFault</span></div>
<div class="line"><a id="l00616" name="l00616"></a><span class="lineno">  616</span>    <span class="comment">// 0x000000e0 [7:5]   PRI_4_3      (0x0) Priority of system handler 4, SecureFault</span></div>
<div class="line"><a id="l00617" name="l00617"></a><span class="lineno">  617</span>    io_rw_32 shpr[3];</div>
<div class="line"><a id="l00618" name="l00618"></a><span class="lineno">  618</span> </div>
<div class="line"><a id="l00619" name="l00619"></a><span class="lineno">  619</span>    _REG_(M33_SHCSR_OFFSET) <span class="comment">// M33_SHCSR</span></div>
<div class="line"><a id="l00620" name="l00620"></a><span class="lineno">  620</span>    <span class="comment">// Provides access to the active and pending status of system exceptions</span></div>
<div class="line"><a id="l00621" name="l00621"></a><span class="lineno">  621</span>    <span class="comment">// 0x00200000 [21]    HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS</span></div>
<div class="line"><a id="l00622" name="l00622"></a><span class="lineno">  622</span>    <span class="comment">// 0x00100000 [20]    SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception</span></div>
<div class="line"><a id="l00623" name="l00623"></a><span class="lineno">  623</span>    <span class="comment">// 0x00080000 [19]    SECUREFAULTENA (0) `DW the SecureFault exception is enabled</span></div>
<div class="line"><a id="l00624" name="l00624"></a><span class="lineno">  624</span>    <span class="comment">// 0x00040000 [18]    USGFAULTENA  (0) `DW the UsageFault exception is enabled `FTSSS</span></div>
<div class="line"><a id="l00625" name="l00625"></a><span class="lineno">  625</span>    <span class="comment">// 0x00020000 [17]    BUSFAULTENA  (0) `DW the BusFault exception is enabled</span></div>
<div class="line"><a id="l00626" name="l00626"></a><span class="lineno">  626</span>    <span class="comment">// 0x00010000 [16]    MEMFAULTENA  (0) `DW the MemManage exception is enabled `FTSSS</span></div>
<div class="line"><a id="l00627" name="l00627"></a><span class="lineno">  627</span>    <span class="comment">// 0x00008000 [15]    SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS</span></div>
<div class="line"><a id="l00628" name="l00628"></a><span class="lineno">  628</span>    <span class="comment">// 0x00004000 [14]    BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception</span></div>
<div class="line"><a id="l00629" name="l00629"></a><span class="lineno">  629</span>    <span class="comment">// 0x00002000 [13]    MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS</span></div>
<div class="line"><a id="l00630" name="l00630"></a><span class="lineno">  630</span>    <span class="comment">// 0x00001000 [12]    USGFAULTPENDED (0) The UsageFault exception is banked between Security...</span></div>
<div class="line"><a id="l00631" name="l00631"></a><span class="lineno">  631</span>    <span class="comment">// 0x00000800 [11]    SYSTICKACT   (0) `IAAMO the active state of the SysTick exception `FTSSS</span></div>
<div class="line"><a id="l00632" name="l00632"></a><span class="lineno">  632</span>    <span class="comment">// 0x00000400 [10]    PENDSVACT    (0) `IAAMO the active state of the PendSV exception `FTSSS</span></div>
<div class="line"><a id="l00633" name="l00633"></a><span class="lineno">  633</span>    <span class="comment">// 0x00000100 [8]     MONITORACT   (0) `IAAMO the active state of the DebugMonitor exception</span></div>
<div class="line"><a id="l00634" name="l00634"></a><span class="lineno">  634</span>    <span class="comment">// 0x00000080 [7]     SVCALLACT    (0) `IAAMO the active state of the SVCall exception `FTSSS</span></div>
<div class="line"><a id="l00635" name="l00635"></a><span class="lineno">  635</span>    <span class="comment">// 0x00000020 [5]     NMIACT       (0) `IAAMO the active state of the NMI exception</span></div>
<div class="line"><a id="l00636" name="l00636"></a><span class="lineno">  636</span>    <span class="comment">// 0x00000010 [4]     SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception</span></div>
<div class="line"><a id="l00637" name="l00637"></a><span class="lineno">  637</span>    <span class="comment">// 0x00000008 [3]     USGFAULTACT  (0) `IAAMO the active state of the UsageFault exception `FTSSS</span></div>
<div class="line"><a id="l00638" name="l00638"></a><span class="lineno">  638</span>    <span class="comment">// 0x00000004 [2]     HARDFAULTACT (0) Indicates and allows limited modification of the active...</span></div>
<div class="line"><a id="l00639" name="l00639"></a><span class="lineno">  639</span>    <span class="comment">// 0x00000002 [1]     BUSFAULTACT  (0) `IAAMO the active state of the BusFault exception</span></div>
<div class="line"><a id="l00640" name="l00640"></a><span class="lineno">  640</span>    <span class="comment">// 0x00000001 [0]     MEMFAULTACT  (0) `IAAMO the active state of the MemManage exception `FTSSS</span></div>
<div class="line"><a id="l00641" name="l00641"></a><span class="lineno">  641</span>    io_rw_32 shcsr;</div>
<div class="line"><a id="l00642" name="l00642"></a><span class="lineno">  642</span> </div>
<div class="line"><a id="l00643" name="l00643"></a><span class="lineno">  643</span>    _REG_(M33_CFSR_OFFSET) <span class="comment">// M33_CFSR</span></div>
<div class="line"><a id="l00644" name="l00644"></a><span class="lineno">  644</span>    <span class="comment">// Contains the three Configurable Fault Status Registers</span></div>
<div class="line"><a id="l00645" name="l00645"></a><span class="lineno">  645</span>    <span class="comment">// 0x02000000 [25]    UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by...</span></div>
<div class="line"><a id="l00646" name="l00646"></a><span class="lineno">  646</span>    <span class="comment">// 0x01000000 [24]    UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error...</span></div>
<div class="line"><a id="l00647" name="l00647"></a><span class="lineno">  647</span>    <span class="comment">// 0x00100000 [20]    UFSR_STKOF   (0) Sticky flag indicating whether a stack overflow error...</span></div>
<div class="line"><a id="l00648" name="l00648"></a><span class="lineno">  648</span>    <span class="comment">// 0x00080000 [19]    UFSR_NOCP    (0) Sticky flag indicating whether a coprocessor disabled or...</span></div>
<div class="line"><a id="l00649" name="l00649"></a><span class="lineno">  649</span>    <span class="comment">// 0x00040000 [18]    UFSR_INVPC   (0) Sticky flag indicating whether an integrity check error...</span></div>
<div class="line"><a id="l00650" name="l00650"></a><span class="lineno">  650</span>    <span class="comment">// 0x00020000 [17]    UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR</span></div>
<div class="line"><a id="l00651" name="l00651"></a><span class="lineno">  651</span>    <span class="comment">// 0x00010000 [16]    UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction...</span></div>
<div class="line"><a id="l00652" name="l00652"></a><span class="lineno">  652</span>    <span class="comment">// 0x00008000 [15]    BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register</span></div>
<div class="line"><a id="l00653" name="l00653"></a><span class="lineno">  653</span>    <span class="comment">// 0x00002000 [13]    BFSR_LSPERR  (0) Records whether a BusFault occurred during FP lazy state...</span></div>
<div class="line"><a id="l00654" name="l00654"></a><span class="lineno">  654</span>    <span class="comment">// 0x00001000 [12]    BFSR_STKERR  (0) Records whether a derived BusFault occurred during...</span></div>
<div class="line"><a id="l00655" name="l00655"></a><span class="lineno">  655</span>    <span class="comment">// 0x00000800 [11]    BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during...</span></div>
<div class="line"><a id="l00656" name="l00656"></a><span class="lineno">  656</span>    <span class="comment">// 0x00000400 [10]    BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred</span></div>
<div class="line"><a id="l00657" name="l00657"></a><span class="lineno">  657</span>    <span class="comment">// 0x00000200 [9]     BFSR_PRECISERR (0) Records whether a precise data access error has occurred</span></div>
<div class="line"><a id="l00658" name="l00658"></a><span class="lineno">  658</span>    <span class="comment">// 0x00000100 [8]     BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch...</span></div>
<div class="line"><a id="l00659" name="l00659"></a><span class="lineno">  659</span>    <span class="comment">// 0x000000ff [7:0]   MMFSR        (0x00) Provides information on MemManage exceptions</span></div>
<div class="line"><a id="l00660" name="l00660"></a><span class="lineno">  660</span>    io_rw_32 cfsr;</div>
<div class="line"><a id="l00661" name="l00661"></a><span class="lineno">  661</span> </div>
<div class="line"><a id="l00662" name="l00662"></a><span class="lineno">  662</span>    _REG_(M33_HFSR_OFFSET) <span class="comment">// M33_HFSR</span></div>
<div class="line"><a id="l00663" name="l00663"></a><span class="lineno">  663</span>    <span class="comment">// Shows the cause of any HardFaults</span></div>
<div class="line"><a id="l00664" name="l00664"></a><span class="lineno">  664</span>    <span class="comment">// 0x80000000 [31]    DEBUGEVT     (0) Indicates when a Debug event has occurred</span></div>
<div class="line"><a id="l00665" name="l00665"></a><span class="lineno">  665</span>    <span class="comment">// 0x40000000 [30]    FORCED       (0) Indicates that a fault with configurable priority has...</span></div>
<div class="line"><a id="l00666" name="l00666"></a><span class="lineno">  666</span>    <span class="comment">// 0x00000002 [1]     VECTTBL      (0) Indicates when a fault has occurred because of a vector...</span></div>
<div class="line"><a id="l00667" name="l00667"></a><span class="lineno">  667</span>    io_rw_32 hfsr;</div>
<div class="line"><a id="l00668" name="l00668"></a><span class="lineno">  668</span> </div>
<div class="line"><a id="l00669" name="l00669"></a><span class="lineno">  669</span>    _REG_(M33_DFSR_OFFSET) <span class="comment">// M33_DFSR</span></div>
<div class="line"><a id="l00670" name="l00670"></a><span class="lineno">  670</span>    <span class="comment">// Shows which debug event occurred</span></div>
<div class="line"><a id="l00671" name="l00671"></a><span class="lineno">  671</span>    <span class="comment">// 0x00000010 [4]     EXTERNAL     (0) Sticky flag indicating whether an External debug request...</span></div>
<div class="line"><a id="l00672" name="l00672"></a><span class="lineno">  672</span>    <span class="comment">// 0x00000008 [3]     VCATCH       (0) Sticky flag indicating whether a Vector catch debug...</span></div>
<div class="line"><a id="l00673" name="l00673"></a><span class="lineno">  673</span>    <span class="comment">// 0x00000004 [2]     DWTTRAP      (0) Sticky flag indicating whether a Watchpoint debug event...</span></div>
<div class="line"><a id="l00674" name="l00674"></a><span class="lineno">  674</span>    <span class="comment">// 0x00000002 [1]     BKPT         (0) Sticky flag indicating whether a Breakpoint debug event...</span></div>
<div class="line"><a id="l00675" name="l00675"></a><span class="lineno">  675</span>    <span class="comment">// 0x00000001 [0]     HALTED       (0) Sticky flag indicating that a Halt request debug event...</span></div>
<div class="line"><a id="l00676" name="l00676"></a><span class="lineno">  676</span>    io_rw_32 dfsr;</div>
<div class="line"><a id="l00677" name="l00677"></a><span class="lineno">  677</span> </div>
<div class="line"><a id="l00678" name="l00678"></a><span class="lineno">  678</span>    _REG_(M33_MMFAR_OFFSET) <span class="comment">// M33_MMFAR</span></div>
<div class="line"><a id="l00679" name="l00679"></a><span class="lineno">  679</span>    <span class="comment">// Shows the address of the memory location that caused an MPU fault</span></div>
<div class="line"><a id="l00680" name="l00680"></a><span class="lineno">  680</span>    <span class="comment">// 0xffffffff [31:0]  ADDRESS      (0x00000000) This register is updated with the address of a location...</span></div>
<div class="line"><a id="l00681" name="l00681"></a><span class="lineno">  681</span>    io_rw_32 mmfar;</div>
<div class="line"><a id="l00682" name="l00682"></a><span class="lineno">  682</span> </div>
<div class="line"><a id="l00683" name="l00683"></a><span class="lineno">  683</span>    _REG_(M33_BFAR_OFFSET) <span class="comment">// M33_BFAR</span></div>
<div class="line"><a id="l00684" name="l00684"></a><span class="lineno">  684</span>    <span class="comment">// Shows the address associated with a precise data access BusFault</span></div>
<div class="line"><a id="l00685" name="l00685"></a><span class="lineno">  685</span>    <span class="comment">// 0xffffffff [31:0]  ADDRESS      (0x00000000) This register is updated with the address of a location...</span></div>
<div class="line"><a id="l00686" name="l00686"></a><span class="lineno">  686</span>    io_rw_32 bfar;</div>
<div class="line"><a id="l00687" name="l00687"></a><span class="lineno">  687</span> </div>
<div class="line"><a id="l00688" name="l00688"></a><span class="lineno">  688</span>    uint32_t _pad32;</div>
<div class="line"><a id="l00689" name="l00689"></a><span class="lineno">  689</span> </div>
<div class="line"><a id="l00690" name="l00690"></a><span class="lineno">  690</span>    <span class="comment">// (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00691" name="l00691"></a><span class="lineno">  691</span>    _REG_(M33_ID_PFR0_OFFSET) <span class="comment">// M33_ID_PFR0</span></div>
<div class="line"><a id="l00692" name="l00692"></a><span class="lineno">  692</span>    <span class="comment">// Gives top-level information about the instruction set supported by the PE</span></div>
<div class="line"><a id="l00693" name="l00693"></a><span class="lineno">  693</span>    <span class="comment">// 0x000000f0 [7:4]   STATE1       (0x3) T32 instruction set support</span></div>
<div class="line"><a id="l00694" name="l00694"></a><span class="lineno">  694</span>    <span class="comment">// 0x0000000f [3:0]   STATE0       (0x0) A32 instruction set support</span></div>
<div class="line"><a id="l00695" name="l00695"></a><span class="lineno">  695</span>    io_ro_32 id_pfr[2];</div>
<div class="line"><a id="l00696" name="l00696"></a><span class="lineno">  696</span> </div>
<div class="line"><a id="l00697" name="l00697"></a><span class="lineno">  697</span>    _REG_(M33_ID_DFR0_OFFSET) <span class="comment">// M33_ID_DFR0</span></div>
<div class="line"><a id="l00698" name="l00698"></a><span class="lineno">  698</span>    <span class="comment">// Provides top level information about the debug system</span></div>
<div class="line"><a id="l00699" name="l00699"></a><span class="lineno">  699</span>    <span class="comment">// 0x00f00000 [23:20] MPROFDBG     (0x2) Indicates the supported M-profile debug architecture</span></div>
<div class="line"><a id="l00700" name="l00700"></a><span class="lineno">  700</span>    io_ro_32 id_dfr0;</div>
<div class="line"><a id="l00701" name="l00701"></a><span class="lineno">  701</span> </div>
<div class="line"><a id="l00702" name="l00702"></a><span class="lineno">  702</span>    _REG_(M33_ID_AFR0_OFFSET) <span class="comment">// M33_ID_AFR0</span></div>
<div class="line"><a id="l00703" name="l00703"></a><span class="lineno">  703</span>    <span class="comment">// Provides information about the IMPLEMENTATION DEFINED features of the PE</span></div>
<div class="line"><a id="l00704" name="l00704"></a><span class="lineno">  704</span>    <span class="comment">// 0x0000f000 [15:12] IMPDEF3      (0x0) IMPLEMENTATION DEFINED meaning</span></div>
<div class="line"><a id="l00705" name="l00705"></a><span class="lineno">  705</span>    <span class="comment">// 0x00000f00 [11:8]  IMPDEF2      (0x0) IMPLEMENTATION DEFINED meaning</span></div>
<div class="line"><a id="l00706" name="l00706"></a><span class="lineno">  706</span>    <span class="comment">// 0x000000f0 [7:4]   IMPDEF1      (0x0) IMPLEMENTATION DEFINED meaning</span></div>
<div class="line"><a id="l00707" name="l00707"></a><span class="lineno">  707</span>    <span class="comment">// 0x0000000f [3:0]   IMPDEF0      (0x0) IMPLEMENTATION DEFINED meaning</span></div>
<div class="line"><a id="l00708" name="l00708"></a><span class="lineno">  708</span>    io_ro_32 id_afr0;</div>
<div class="line"><a id="l00709" name="l00709"></a><span class="lineno">  709</span> </div>
<div class="line"><a id="l00710" name="l00710"></a><span class="lineno">  710</span>    <span class="comment">// (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00711" name="l00711"></a><span class="lineno">  711</span>    _REG_(M33_ID_MMFR0_OFFSET) <span class="comment">// M33_ID_MMFR0</span></div>
<div class="line"><a id="l00712" name="l00712"></a><span class="lineno">  712</span>    <span class="comment">// Provides information about the implemented memory model and memory management support</span></div>
<div class="line"><a id="l00713" name="l00713"></a><span class="lineno">  713</span>    <span class="comment">// 0x00f00000 [23:20] AUXREG       (0x1) Indicates support for Auxiliary Control Registers</span></div>
<div class="line"><a id="l00714" name="l00714"></a><span class="lineno">  714</span>    <span class="comment">// 0x000f0000 [19:16] TCM          (0x0) Indicates support for tightly coupled memories (TCMs)</span></div>
<div class="line"><a id="l00715" name="l00715"></a><span class="lineno">  715</span>    <span class="comment">// 0x0000f000 [15:12] SHARELVL     (0x1) Indicates the number of shareability levels implemented</span></div>
<div class="line"><a id="l00716" name="l00716"></a><span class="lineno">  716</span>    <span class="comment">// 0x00000f00 [11:8]  OUTERSHR     (0xf) Indicates the outermost shareability domain implemented</span></div>
<div class="line"><a id="l00717" name="l00717"></a><span class="lineno">  717</span>    <span class="comment">// 0x000000f0 [7:4]   PMSA         (0x4) Indicates support for the protected memory system...</span></div>
<div class="line"><a id="l00718" name="l00718"></a><span class="lineno">  718</span>    io_ro_32 id_mmfr[4];</div>
<div class="line"><a id="l00719" name="l00719"></a><span class="lineno">  719</span> </div>
<div class="line"><a id="l00720" name="l00720"></a><span class="lineno">  720</span>    <span class="comment">// (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00721" name="l00721"></a><span class="lineno">  721</span>    _REG_(M33_ID_ISAR0_OFFSET) <span class="comment">// M33_ID_ISAR0</span></div>
<div class="line"><a id="l00722" name="l00722"></a><span class="lineno">  722</span>    <span class="comment">// Provides information about the instruction set implemented by the PE</span></div>
<div class="line"><a id="l00723" name="l00723"></a><span class="lineno">  723</span>    <span class="comment">// 0x0f000000 [27:24] DIVIDE       (0x8) Indicates the supported Divide instructions</span></div>
<div class="line"><a id="l00724" name="l00724"></a><span class="lineno">  724</span>    <span class="comment">// 0x00f00000 [23:20] DEBUG        (0x0) Indicates the implemented Debug instructions</span></div>
<div class="line"><a id="l00725" name="l00725"></a><span class="lineno">  725</span>    <span class="comment">// 0x000f0000 [19:16] COPROC       (0x9) Indicates the supported Coprocessor instructions</span></div>
<div class="line"><a id="l00726" name="l00726"></a><span class="lineno">  726</span>    <span class="comment">// 0x0000f000 [15:12] CMPBRANCH    (0x2) Indicates the supported combined Compare and Branch instructions</span></div>
<div class="line"><a id="l00727" name="l00727"></a><span class="lineno">  727</span>    <span class="comment">// 0x00000f00 [11:8]  BITFIELD     (0x3) Indicates the supported bit field instructions</span></div>
<div class="line"><a id="l00728" name="l00728"></a><span class="lineno">  728</span>    <span class="comment">// 0x000000f0 [7:4]   BITCOUNT     (0x0) Indicates the supported bit count instructions</span></div>
<div class="line"><a id="l00729" name="l00729"></a><span class="lineno">  729</span>    io_ro_32 id_isar[6];</div>
<div class="line"><a id="l00730" name="l00730"></a><span class="lineno">  730</span> </div>
<div class="line"><a id="l00731" name="l00731"></a><span class="lineno">  731</span>    uint32_t _pad33;</div>
<div class="line"><a id="l00732" name="l00732"></a><span class="lineno">  732</span> </div>
<div class="line"><a id="l00733" name="l00733"></a><span class="lineno">  733</span>    _REG_(M33_CTR_OFFSET) <span class="comment">// M33_CTR</span></div>
<div class="line"><a id="l00734" name="l00734"></a><span class="lineno">  734</span>    <span class="comment">// Provides information about the architecture of the caches</span></div>
<div class="line"><a id="l00735" name="l00735"></a><span class="lineno">  735</span>    <span class="comment">// 0x80000000 [31]    RES1         (1) Reserved, RES1</span></div>
<div class="line"><a id="l00736" name="l00736"></a><span class="lineno">  736</span>    <span class="comment">// 0x0f000000 [27:24] CWG          (0x0) Log2 of the number of words of the maximum size of...</span></div>
<div class="line"><a id="l00737" name="l00737"></a><span class="lineno">  737</span>    <span class="comment">// 0x00f00000 [23:20] ERG          (0x0) Log2 of the number of words of the maximum size of the...</span></div>
<div class="line"><a id="l00738" name="l00738"></a><span class="lineno">  738</span>    <span class="comment">// 0x000f0000 [19:16] DMINLINE     (0x0) Log2 of the number of words in the smallest cache line...</span></div>
<div class="line"><a id="l00739" name="l00739"></a><span class="lineno">  739</span>    <span class="comment">// 0x0000c000 [15:14] RES1_1       (0x3) Reserved, RES1</span></div>
<div class="line"><a id="l00740" name="l00740"></a><span class="lineno">  740</span>    <span class="comment">// 0x0000000f [3:0]   IMINLINE     (0x0) Log2 of the number of words in the smallest cache line...</span></div>
<div class="line"><a id="l00741" name="l00741"></a><span class="lineno">  741</span>    io_ro_32 ctr;</div>
<div class="line"><a id="l00742" name="l00742"></a><span class="lineno">  742</span> </div>
<div class="line"><a id="l00743" name="l00743"></a><span class="lineno">  743</span>    uint32_t _pad34[2];</div>
<div class="line"><a id="l00744" name="l00744"></a><span class="lineno">  744</span> </div>
<div class="line"><a id="l00745" name="l00745"></a><span class="lineno">  745</span>    _REG_(M33_CPACR_OFFSET) <span class="comment">// M33_CPACR</span></div>
<div class="line"><a id="l00746" name="l00746"></a><span class="lineno">  746</span>    <span class="comment">// Specifies the access privileges for coprocessors and the FP Extension</span></div>
<div class="line"><a id="l00747" name="l00747"></a><span class="lineno">  747</span>    <span class="comment">// 0x00c00000 [23:22] CP11         (0x0) The value in this field is ignored</span></div>
<div class="line"><a id="l00748" name="l00748"></a><span class="lineno">  748</span>    <span class="comment">// 0x00300000 [21:20] CP10         (0x0) Defines the access rights for the floating-point functionality</span></div>
<div class="line"><a id="l00749" name="l00749"></a><span class="lineno">  749</span>    <span class="comment">// 0x0000c000 [15:14] CP7          (0x0) Controls access privileges for coprocessor 7</span></div>
<div class="line"><a id="l00750" name="l00750"></a><span class="lineno">  750</span>    <span class="comment">// 0x00003000 [13:12] CP6          (0x0) Controls access privileges for coprocessor 6</span></div>
<div class="line"><a id="l00751" name="l00751"></a><span class="lineno">  751</span>    <span class="comment">// 0x00000c00 [11:10] CP5          (0x0) Controls access privileges for coprocessor 5</span></div>
<div class="line"><a id="l00752" name="l00752"></a><span class="lineno">  752</span>    <span class="comment">// 0x00000300 [9:8]   CP4          (0x0) Controls access privileges for coprocessor 4</span></div>
<div class="line"><a id="l00753" name="l00753"></a><span class="lineno">  753</span>    <span class="comment">// 0x000000c0 [7:6]   CP3          (0x0) Controls access privileges for coprocessor 3</span></div>
<div class="line"><a id="l00754" name="l00754"></a><span class="lineno">  754</span>    <span class="comment">// 0x00000030 [5:4]   CP2          (0x0) Controls access privileges for coprocessor 2</span></div>
<div class="line"><a id="l00755" name="l00755"></a><span class="lineno">  755</span>    <span class="comment">// 0x0000000c [3:2]   CP1          (0x0) Controls access privileges for coprocessor 1</span></div>
<div class="line"><a id="l00756" name="l00756"></a><span class="lineno">  756</span>    <span class="comment">// 0x00000003 [1:0]   CP0          (0x0) Controls access privileges for coprocessor 0</span></div>
<div class="line"><a id="l00757" name="l00757"></a><span class="lineno">  757</span>    io_rw_32 cpacr;</div>
<div class="line"><a id="l00758" name="l00758"></a><span class="lineno">  758</span> </div>
<div class="line"><a id="l00759" name="l00759"></a><span class="lineno">  759</span>    _REG_(M33_NSACR_OFFSET) <span class="comment">// M33_NSACR</span></div>
<div class="line"><a id="l00760" name="l00760"></a><span class="lineno">  760</span>    <span class="comment">// Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7</span></div>
<div class="line"><a id="l00761" name="l00761"></a><span class="lineno">  761</span>    <span class="comment">// 0x00000800 [11]    CP11         (0) Enables Non-secure access to the Floating-point Extension</span></div>
<div class="line"><a id="l00762" name="l00762"></a><span class="lineno">  762</span>    <span class="comment">// 0x00000400 [10]    CP10         (0) Enables Non-secure access to the Floating-point Extension</span></div>
<div class="line"><a id="l00763" name="l00763"></a><span class="lineno">  763</span>    <span class="comment">// 0x00000080 [7]     CP7          (0) Enables Non-secure access to coprocessor CP7</span></div>
<div class="line"><a id="l00764" name="l00764"></a><span class="lineno">  764</span>    <span class="comment">// 0x00000040 [6]     CP6          (0) Enables Non-secure access to coprocessor CP6</span></div>
<div class="line"><a id="l00765" name="l00765"></a><span class="lineno">  765</span>    <span class="comment">// 0x00000020 [5]     CP5          (0) Enables Non-secure access to coprocessor CP5</span></div>
<div class="line"><a id="l00766" name="l00766"></a><span class="lineno">  766</span>    <span class="comment">// 0x00000010 [4]     CP4          (0) Enables Non-secure access to coprocessor CP4</span></div>
<div class="line"><a id="l00767" name="l00767"></a><span class="lineno">  767</span>    <span class="comment">// 0x00000008 [3]     CP3          (0) Enables Non-secure access to coprocessor CP3</span></div>
<div class="line"><a id="l00768" name="l00768"></a><span class="lineno">  768</span>    <span class="comment">// 0x00000004 [2]     CP2          (0) Enables Non-secure access to coprocessor CP2</span></div>
<div class="line"><a id="l00769" name="l00769"></a><span class="lineno">  769</span>    <span class="comment">// 0x00000002 [1]     CP1          (0) Enables Non-secure access to coprocessor CP1</span></div>
<div class="line"><a id="l00770" name="l00770"></a><span class="lineno">  770</span>    <span class="comment">// 0x00000001 [0]     CP0          (0) Enables Non-secure access to coprocessor CP0</span></div>
<div class="line"><a id="l00771" name="l00771"></a><span class="lineno">  771</span>    io_rw_32 nsacr;</div>
<div class="line"><a id="l00772" name="l00772"></a><span class="lineno">  772</span> </div>
<div class="line"><a id="l00773" name="l00773"></a><span class="lineno">  773</span>    _REG_(M33_MPU_TYPE_OFFSET) <span class="comment">// M33_MPU_TYPE</span></div>
<div class="line"><a id="l00774" name="l00774"></a><span class="lineno">  774</span>    <span class="comment">// The MPU Type Register indicates how many regions the MPU `FTSSS supports</span></div>
<div class="line"><a id="l00775" name="l00775"></a><span class="lineno">  775</span>    <span class="comment">// 0x0000ff00 [15:8]  DREGION      (0x08) Number of regions supported by the MPU</span></div>
<div class="line"><a id="l00776" name="l00776"></a><span class="lineno">  776</span>    <span class="comment">// 0x00000001 [0]     SEPARATE     (0) Indicates support for separate instructions and data...</span></div>
<div class="line"><a id="l00777" name="l00777"></a><span class="lineno">  777</span>    io_ro_32 mpu_type;</div>
<div class="line"><a id="l00778" name="l00778"></a><span class="lineno">  778</span> </div>
<div class="line"><a id="l00779" name="l00779"></a><span class="lineno">  779</span>    _REG_(M33_MPU_CTRL_OFFSET) <span class="comment">// M33_MPU_CTRL</span></div>
<div class="line"><a id="l00780" name="l00780"></a><span class="lineno">  780</span>    <span class="comment">// Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled...</span></div>
<div class="line"><a id="l00781" name="l00781"></a><span class="lineno">  781</span>    <span class="comment">// 0x00000004 [2]     PRIVDEFENA   (0) Controls whether the default memory map is enabled for...</span></div>
<div class="line"><a id="l00782" name="l00782"></a><span class="lineno">  782</span>    <span class="comment">// 0x00000002 [1]     HFNMIENA     (0) Controls whether handlers executing with priority less...</span></div>
<div class="line"><a id="l00783" name="l00783"></a><span class="lineno">  783</span>    <span class="comment">// 0x00000001 [0]     ENABLE       (0) Enables the MPU</span></div>
<div class="line"><a id="l00784" name="l00784"></a><span class="lineno">  784</span>    io_rw_32 mpu_ctrl;</div>
<div class="line"><a id="l00785" name="l00785"></a><span class="lineno">  785</span> </div>
<div class="line"><a id="l00786" name="l00786"></a><span class="lineno">  786</span>    _REG_(M33_MPU_RNR_OFFSET) <span class="comment">// M33_MPU_RNR</span></div>
<div class="line"><a id="l00787" name="l00787"></a><span class="lineno">  787</span>    <span class="comment">// Selects the region currently accessed by MPU_RBAR and MPU_RLAR</span></div>
<div class="line"><a id="l00788" name="l00788"></a><span class="lineno">  788</span>    <span class="comment">// 0x00000007 [2:0]   REGION       (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR</span></div>
<div class="line"><a id="l00789" name="l00789"></a><span class="lineno">  789</span>    io_rw_32 mpu_rnr;</div>
<div class="line"><a id="l00790" name="l00790"></a><span class="lineno">  790</span> </div>
<div class="line"><a id="l00791" name="l00791"></a><span class="lineno">  791</span>    _REG_(M33_MPU_RBAR_OFFSET) <span class="comment">// M33_MPU_RBAR</span></div>
<div class="line"><a id="l00792" name="l00792"></a><span class="lineno">  792</span>    <span class="comment">// Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS</span></div>
<div class="line"><a id="l00793" name="l00793"></a><span class="lineno">  793</span>    <span class="comment">// 0xffffffe0 [31:5]  BASE         (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...</span></div>
<div class="line"><a id="l00794" name="l00794"></a><span class="lineno">  794</span>    <span class="comment">// 0x00000018 [4:3]   SH           (0x0) Defines the Shareability domain of this region for Normal memory</span></div>
<div class="line"><a id="l00795" name="l00795"></a><span class="lineno">  795</span>    <span class="comment">// 0x00000006 [2:1]   AP           (0x0) Defines the access permissions for this region</span></div>
<div class="line"><a id="l00796" name="l00796"></a><span class="lineno">  796</span>    <span class="comment">// 0x00000001 [0]     XN           (0) Defines whether code can be executed from this region</span></div>
<div class="line"><a id="l00797" name="l00797"></a><span class="lineno">  797</span>    io_rw_32 mpu_rbar;</div>
<div class="line"><a id="l00798" name="l00798"></a><span class="lineno">  798</span> </div>
<div class="line"><a id="l00799" name="l00799"></a><span class="lineno">  799</span>    _REG_(M33_MPU_RLAR_OFFSET) <span class="comment">// M33_MPU_RLAR</span></div>
<div class="line"><a id="l00800" name="l00800"></a><span class="lineno">  800</span>    <span class="comment">// Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS</span></div>
<div class="line"><a id="l00801" name="l00801"></a><span class="lineno">  801</span>    <span class="comment">// 0xffffffe0 [31:5]  LIMIT        (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...</span></div>
<div class="line"><a id="l00802" name="l00802"></a><span class="lineno">  802</span>    <span class="comment">// 0x0000000e [3:1]   ATTRINDX     (0x0) Associates a set of attributes in the MPU_MAIR0 and...</span></div>
<div class="line"><a id="l00803" name="l00803"></a><span class="lineno">  803</span>    <span class="comment">// 0x00000001 [0]     EN           (0) Region enable</span></div>
<div class="line"><a id="l00804" name="l00804"></a><span class="lineno">  804</span>    io_rw_32 mpu_rlar;</div>
<div class="line"><a id="l00805" name="l00805"></a><span class="lineno">  805</span> </div>
<div class="line"><a id="l00806" name="l00806"></a><span class="lineno">  806</span>    _REG_(M33_MPU_RBAR_A1_OFFSET) <span class="comment">// M33_MPU_RBAR_A1</span></div>
<div class="line"><a id="l00807" name="l00807"></a><span class="lineno">  807</span>    <span class="comment">// Provides indirect read and write access to the base address of the MPU region selected by...</span></div>
<div class="line"><a id="l00808" name="l00808"></a><span class="lineno">  808</span>    <span class="comment">// 0xffffffe0 [31:5]  BASE         (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...</span></div>
<div class="line"><a id="l00809" name="l00809"></a><span class="lineno">  809</span>    <span class="comment">// 0x00000018 [4:3]   SH           (0x0) Defines the Shareability domain of this region for Normal memory</span></div>
<div class="line"><a id="l00810" name="l00810"></a><span class="lineno">  810</span>    <span class="comment">// 0x00000006 [2:1]   AP           (0x0) Defines the access permissions for this region</span></div>
<div class="line"><a id="l00811" name="l00811"></a><span class="lineno">  811</span>    <span class="comment">// 0x00000001 [0]     XN           (0) Defines whether code can be executed from this region</span></div>
<div class="line"><a id="l00812" name="l00812"></a><span class="lineno">  812</span>    io_rw_32 mpu_rbar_a1;</div>
<div class="line"><a id="l00813" name="l00813"></a><span class="lineno">  813</span> </div>
<div class="line"><a id="l00814" name="l00814"></a><span class="lineno">  814</span>    _REG_(M33_MPU_RLAR_A1_OFFSET) <span class="comment">// M33_MPU_RLAR_A1</span></div>
<div class="line"><a id="l00815" name="l00815"></a><span class="lineno">  815</span>    <span class="comment">// Provides indirect read and write access to the limit address of the currently selected MPU...</span></div>
<div class="line"><a id="l00816" name="l00816"></a><span class="lineno">  816</span>    <span class="comment">// 0xffffffe0 [31:5]  LIMIT        (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...</span></div>
<div class="line"><a id="l00817" name="l00817"></a><span class="lineno">  817</span>    <span class="comment">// 0x0000000e [3:1]   ATTRINDX     (0x0) Associates a set of attributes in the MPU_MAIR0 and...</span></div>
<div class="line"><a id="l00818" name="l00818"></a><span class="lineno">  818</span>    <span class="comment">// 0x00000001 [0]     EN           (0) Region enable</span></div>
<div class="line"><a id="l00819" name="l00819"></a><span class="lineno">  819</span>    io_rw_32 mpu_rlar_a1;</div>
<div class="line"><a id="l00820" name="l00820"></a><span class="lineno">  820</span> </div>
<div class="line"><a id="l00821" name="l00821"></a><span class="lineno">  821</span>    _REG_(M33_MPU_RBAR_A2_OFFSET) <span class="comment">// M33_MPU_RBAR_A2</span></div>
<div class="line"><a id="l00822" name="l00822"></a><span class="lineno">  822</span>    <span class="comment">// Provides indirect read and write access to the base address of the MPU region selected by...</span></div>
<div class="line"><a id="l00823" name="l00823"></a><span class="lineno">  823</span>    <span class="comment">// 0xffffffe0 [31:5]  BASE         (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...</span></div>
<div class="line"><a id="l00824" name="l00824"></a><span class="lineno">  824</span>    <span class="comment">// 0x00000018 [4:3]   SH           (0x0) Defines the Shareability domain of this region for Normal memory</span></div>
<div class="line"><a id="l00825" name="l00825"></a><span class="lineno">  825</span>    <span class="comment">// 0x00000006 [2:1]   AP           (0x0) Defines the access permissions for this region</span></div>
<div class="line"><a id="l00826" name="l00826"></a><span class="lineno">  826</span>    <span class="comment">// 0x00000001 [0]     XN           (0) Defines whether code can be executed from this region</span></div>
<div class="line"><a id="l00827" name="l00827"></a><span class="lineno">  827</span>    io_rw_32 mpu_rbar_a2;</div>
<div class="line"><a id="l00828" name="l00828"></a><span class="lineno">  828</span> </div>
<div class="line"><a id="l00829" name="l00829"></a><span class="lineno">  829</span>    _REG_(M33_MPU_RLAR_A2_OFFSET) <span class="comment">// M33_MPU_RLAR_A2</span></div>
<div class="line"><a id="l00830" name="l00830"></a><span class="lineno">  830</span>    <span class="comment">// Provides indirect read and write access to the limit address of the currently selected MPU...</span></div>
<div class="line"><a id="l00831" name="l00831"></a><span class="lineno">  831</span>    <span class="comment">// 0xffffffe0 [31:5]  LIMIT        (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...</span></div>
<div class="line"><a id="l00832" name="l00832"></a><span class="lineno">  832</span>    <span class="comment">// 0x0000000e [3:1]   ATTRINDX     (0x0) Associates a set of attributes in the MPU_MAIR0 and...</span></div>
<div class="line"><a id="l00833" name="l00833"></a><span class="lineno">  833</span>    <span class="comment">// 0x00000001 [0]     EN           (0) Region enable</span></div>
<div class="line"><a id="l00834" name="l00834"></a><span class="lineno">  834</span>    io_rw_32 mpu_rlar_a2;</div>
<div class="line"><a id="l00835" name="l00835"></a><span class="lineno">  835</span> </div>
<div class="line"><a id="l00836" name="l00836"></a><span class="lineno">  836</span>    _REG_(M33_MPU_RBAR_A3_OFFSET) <span class="comment">// M33_MPU_RBAR_A3</span></div>
<div class="line"><a id="l00837" name="l00837"></a><span class="lineno">  837</span>    <span class="comment">// Provides indirect read and write access to the base address of the MPU region selected by...</span></div>
<div class="line"><a id="l00838" name="l00838"></a><span class="lineno">  838</span>    <span class="comment">// 0xffffffe0 [31:5]  BASE         (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...</span></div>
<div class="line"><a id="l00839" name="l00839"></a><span class="lineno">  839</span>    <span class="comment">// 0x00000018 [4:3]   SH           (0x0) Defines the Shareability domain of this region for Normal memory</span></div>
<div class="line"><a id="l00840" name="l00840"></a><span class="lineno">  840</span>    <span class="comment">// 0x00000006 [2:1]   AP           (0x0) Defines the access permissions for this region</span></div>
<div class="line"><a id="l00841" name="l00841"></a><span class="lineno">  841</span>    <span class="comment">// 0x00000001 [0]     XN           (0) Defines whether code can be executed from this region</span></div>
<div class="line"><a id="l00842" name="l00842"></a><span class="lineno">  842</span>    io_rw_32 mpu_rbar_a3;</div>
<div class="line"><a id="l00843" name="l00843"></a><span class="lineno">  843</span> </div>
<div class="line"><a id="l00844" name="l00844"></a><span class="lineno">  844</span>    _REG_(M33_MPU_RLAR_A3_OFFSET) <span class="comment">// M33_MPU_RLAR_A3</span></div>
<div class="line"><a id="l00845" name="l00845"></a><span class="lineno">  845</span>    <span class="comment">// Provides indirect read and write access to the limit address of the currently selected MPU...</span></div>
<div class="line"><a id="l00846" name="l00846"></a><span class="lineno">  846</span>    <span class="comment">// 0xffffffe0 [31:5]  LIMIT        (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...</span></div>
<div class="line"><a id="l00847" name="l00847"></a><span class="lineno">  847</span>    <span class="comment">// 0x0000000e [3:1]   ATTRINDX     (0x0) Associates a set of attributes in the MPU_MAIR0 and...</span></div>
<div class="line"><a id="l00848" name="l00848"></a><span class="lineno">  848</span>    <span class="comment">// 0x00000001 [0]     EN           (0) Region enable</span></div>
<div class="line"><a id="l00849" name="l00849"></a><span class="lineno">  849</span>    io_rw_32 mpu_rlar_a3;</div>
<div class="line"><a id="l00850" name="l00850"></a><span class="lineno">  850</span> </div>
<div class="line"><a id="l00851" name="l00851"></a><span class="lineno">  851</span>    uint32_t _pad35;</div>
<div class="line"><a id="l00852" name="l00852"></a><span class="lineno">  852</span> </div>
<div class="line"><a id="l00853" name="l00853"></a><span class="lineno">  853</span>    <span class="comment">// (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00854" name="l00854"></a><span class="lineno">  854</span>    _REG_(M33_MPU_MAIR0_OFFSET) <span class="comment">// M33_MPU_MAIR0</span></div>
<div class="line"><a id="l00855" name="l00855"></a><span class="lineno">  855</span>    <span class="comment">// Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values</span></div>
<div class="line"><a id="l00856" name="l00856"></a><span class="lineno">  856</span>    <span class="comment">// 0xff000000 [31:24] ATTR3        (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3</span></div>
<div class="line"><a id="l00857" name="l00857"></a><span class="lineno">  857</span>    <span class="comment">// 0x00ff0000 [23:16] ATTR2        (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2</span></div>
<div class="line"><a id="l00858" name="l00858"></a><span class="lineno">  858</span>    <span class="comment">// 0x0000ff00 [15:8]  ATTR1        (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1</span></div>
<div class="line"><a id="l00859" name="l00859"></a><span class="lineno">  859</span>    <span class="comment">// 0x000000ff [7:0]   ATTR0        (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0</span></div>
<div class="line"><a id="l00860" name="l00860"></a><span class="lineno">  860</span>    io_rw_32 mpu_mair[2];</div>
<div class="line"><a id="l00861" name="l00861"></a><span class="lineno">  861</span> </div>
<div class="line"><a id="l00862" name="l00862"></a><span class="lineno">  862</span>    uint32_t _pad36[2];</div>
<div class="line"><a id="l00863" name="l00863"></a><span class="lineno">  863</span> </div>
<div class="line"><a id="l00864" name="l00864"></a><span class="lineno">  864</span>    _REG_(M33_SAU_CTRL_OFFSET) <span class="comment">// M33_SAU_CTRL</span></div>
<div class="line"><a id="l00865" name="l00865"></a><span class="lineno">  865</span>    <span class="comment">// Allows enabling of the Security Attribution Unit</span></div>
<div class="line"><a id="l00866" name="l00866"></a><span class="lineno">  866</span>    <span class="comment">// 0x00000002 [1]     ALLNS        (0) When SAU_CTRL</span></div>
<div class="line"><a id="l00867" name="l00867"></a><span class="lineno">  867</span>    <span class="comment">// 0x00000001 [0]     ENABLE       (0) Enables the SAU</span></div>
<div class="line"><a id="l00868" name="l00868"></a><span class="lineno">  868</span>    io_rw_32 sau_ctrl;</div>
<div class="line"><a id="l00869" name="l00869"></a><span class="lineno">  869</span> </div>
<div class="line"><a id="l00870" name="l00870"></a><span class="lineno">  870</span>    _REG_(M33_SAU_TYPE_OFFSET) <span class="comment">// M33_SAU_TYPE</span></div>
<div class="line"><a id="l00871" name="l00871"></a><span class="lineno">  871</span>    <span class="comment">// Indicates the number of regions implemented by the Security Attribution Unit</span></div>
<div class="line"><a id="l00872" name="l00872"></a><span class="lineno">  872</span>    <span class="comment">// 0x000000ff [7:0]   SREGION      (0x08) The number of implemented SAU regions</span></div>
<div class="line"><a id="l00873" name="l00873"></a><span class="lineno">  873</span>    io_ro_32 sau_type;</div>
<div class="line"><a id="l00874" name="l00874"></a><span class="lineno">  874</span> </div>
<div class="line"><a id="l00875" name="l00875"></a><span class="lineno">  875</span>    _REG_(M33_SAU_RNR_OFFSET) <span class="comment">// M33_SAU_RNR</span></div>
<div class="line"><a id="l00876" name="l00876"></a><span class="lineno">  876</span>    <span class="comment">// Selects the region currently accessed by SAU_RBAR and SAU_RLAR</span></div>
<div class="line"><a id="l00877" name="l00877"></a><span class="lineno">  877</span>    <span class="comment">// 0x000000ff [7:0]   REGION       (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR</span></div>
<div class="line"><a id="l00878" name="l00878"></a><span class="lineno">  878</span>    io_rw_32 sau_rnr;</div>
<div class="line"><a id="l00879" name="l00879"></a><span class="lineno">  879</span> </div>
<div class="line"><a id="l00880" name="l00880"></a><span class="lineno">  880</span>    _REG_(M33_SAU_RBAR_OFFSET) <span class="comment">// M33_SAU_RBAR</span></div>
<div class="line"><a id="l00881" name="l00881"></a><span class="lineno">  881</span>    <span class="comment">// Provides indirect read and write access to the base address of the currently selected SAU region</span></div>
<div class="line"><a id="l00882" name="l00882"></a><span class="lineno">  882</span>    <span class="comment">// 0xffffffe0 [31:5]  BADDR        (0x0000000) Holds bits [31:5] of the base address for the selected SAU region</span></div>
<div class="line"><a id="l00883" name="l00883"></a><span class="lineno">  883</span>    io_rw_32 sau_rbar;</div>
<div class="line"><a id="l00884" name="l00884"></a><span class="lineno">  884</span> </div>
<div class="line"><a id="l00885" name="l00885"></a><span class="lineno">  885</span>    _REG_(M33_SAU_RLAR_OFFSET) <span class="comment">// M33_SAU_RLAR</span></div>
<div class="line"><a id="l00886" name="l00886"></a><span class="lineno">  886</span>    <span class="comment">// Provides indirect read and write access to the limit address of the currently selected SAU region</span></div>
<div class="line"><a id="l00887" name="l00887"></a><span class="lineno">  887</span>    <span class="comment">// 0xffffffe0 [31:5]  LADDR        (0x0000000) Holds bits [31:5] of the limit address for the selected...</span></div>
<div class="line"><a id="l00888" name="l00888"></a><span class="lineno">  888</span>    <span class="comment">// 0x00000002 [1]     NSC          (0) Controls whether Non-secure state is permitted to...</span></div>
<div class="line"><a id="l00889" name="l00889"></a><span class="lineno">  889</span>    <span class="comment">// 0x00000001 [0]     ENABLE       (0) SAU region enable</span></div>
<div class="line"><a id="l00890" name="l00890"></a><span class="lineno">  890</span>    io_rw_32 sau_rlar;</div>
<div class="line"><a id="l00891" name="l00891"></a><span class="lineno">  891</span> </div>
<div class="line"><a id="l00892" name="l00892"></a><span class="lineno">  892</span>    _REG_(M33_SFSR_OFFSET) <span class="comment">// M33_SFSR</span></div>
<div class="line"><a id="l00893" name="l00893"></a><span class="lineno">  893</span>    <span class="comment">// Provides information about any security related faults</span></div>
<div class="line"><a id="l00894" name="l00894"></a><span class="lineno">  894</span>    <span class="comment">// 0x00000080 [7]     LSERR        (0) Sticky flag indicating that an error occurred during...</span></div>
<div class="line"><a id="l00895" name="l00895"></a><span class="lineno">  895</span>    <span class="comment">// 0x00000040 [6]     SFARVALID    (0) This bit is set when the SFAR register contains a valid value</span></div>
<div class="line"><a id="l00896" name="l00896"></a><span class="lineno">  896</span>    <span class="comment">// 0x00000020 [5]     LSPERR       (0) Stick flag indicating that an SAU or IDAU violation...</span></div>
<div class="line"><a id="l00897" name="l00897"></a><span class="lineno">  897</span>    <span class="comment">// 0x00000010 [4]     INVTRAN      (0) Sticky flag indicating that an exception was raised due...</span></div>
<div class="line"><a id="l00898" name="l00898"></a><span class="lineno">  898</span>    <span class="comment">// 0x00000008 [3]     AUVIOL       (0) Sticky flag indicating that an attempt was made to...</span></div>
<div class="line"><a id="l00899" name="l00899"></a><span class="lineno">  899</span>    <span class="comment">// 0x00000004 [2]     INVER        (0) This can be caused by EXC_RETURN</span></div>
<div class="line"><a id="l00900" name="l00900"></a><span class="lineno">  900</span>    <span class="comment">// 0x00000002 [1]     INVIS        (0) This bit is set if the integrity signature in an...</span></div>
<div class="line"><a id="l00901" name="l00901"></a><span class="lineno">  901</span>    <span class="comment">// 0x00000001 [0]     INVEP        (0) This bit is set if a function call from the Non-secure...</span></div>
<div class="line"><a id="l00902" name="l00902"></a><span class="lineno">  902</span>    io_rw_32 sfsr;</div>
<div class="line"><a id="l00903" name="l00903"></a><span class="lineno">  903</span> </div>
<div class="line"><a id="l00904" name="l00904"></a><span class="lineno">  904</span>    _REG_(M33_SFAR_OFFSET) <span class="comment">// M33_SFAR</span></div>
<div class="line"><a id="l00905" name="l00905"></a><span class="lineno">  905</span>    <span class="comment">// Shows the address of the memory location that caused a Security violation</span></div>
<div class="line"><a id="l00906" name="l00906"></a><span class="lineno">  906</span>    <span class="comment">// 0xffffffff [31:0]  ADDRESS      (0x00000000) The address of an access that caused a attribution unit violation</span></div>
<div class="line"><a id="l00907" name="l00907"></a><span class="lineno">  907</span>    io_rw_32 sfar;</div>
<div class="line"><a id="l00908" name="l00908"></a><span class="lineno">  908</span> </div>
<div class="line"><a id="l00909" name="l00909"></a><span class="lineno">  909</span>    uint32_t _pad37;</div>
<div class="line"><a id="l00910" name="l00910"></a><span class="lineno">  910</span> </div>
<div class="line"><a id="l00911" name="l00911"></a><span class="lineno">  911</span>    _REG_(M33_DHCSR_OFFSET) <span class="comment">// M33_DHCSR</span></div>
<div class="line"><a id="l00912" name="l00912"></a><span class="lineno">  912</span>    <span class="comment">// Controls halting debug</span></div>
<div class="line"><a id="l00913" name="l00913"></a><span class="lineno">  913</span>    <span class="comment">// 0x04000000 [26]    S_RESTART_ST (0) Indicates the PE has processed a request to clear DHCSR</span></div>
<div class="line"><a id="l00914" name="l00914"></a><span class="lineno">  914</span>    <span class="comment">// 0x02000000 [25]    S_RESET_ST   (0) Indicates whether the PE has been reset since the last...</span></div>
<div class="line"><a id="l00915" name="l00915"></a><span class="lineno">  915</span>    <span class="comment">// 0x01000000 [24]    S_RETIRE_ST  (0) Set to 1 every time the PE retires one of more instructions</span></div>
<div class="line"><a id="l00916" name="l00916"></a><span class="lineno">  916</span>    <span class="comment">// 0x00100000 [20]    S_SDE        (0) Indicates whether Secure invasive debug is allowed</span></div>
<div class="line"><a id="l00917" name="l00917"></a><span class="lineno">  917</span>    <span class="comment">// 0x00080000 [19]    S_LOCKUP     (0) Indicates whether the PE is in Lockup state</span></div>
<div class="line"><a id="l00918" name="l00918"></a><span class="lineno">  918</span>    <span class="comment">// 0x00040000 [18]    S_SLEEP      (0) Indicates whether the PE is sleeping</span></div>
<div class="line"><a id="l00919" name="l00919"></a><span class="lineno">  919</span>    <span class="comment">// 0x00020000 [17]    S_HALT       (0) Indicates whether the PE is in Debug state</span></div>
<div class="line"><a id="l00920" name="l00920"></a><span class="lineno">  920</span>    <span class="comment">// 0x00010000 [16]    S_REGRDY     (0) Handshake flag to transfers through the DCRDR</span></div>
<div class="line"><a id="l00921" name="l00921"></a><span class="lineno">  921</span>    <span class="comment">// 0x00000020 [5]     C_SNAPSTALL  (0) Allow imprecise entry to Debug state</span></div>
<div class="line"><a id="l00922" name="l00922"></a><span class="lineno">  922</span>    <span class="comment">// 0x00000008 [3]     C_MASKINTS   (0) When debug is enabled, the debugger can write to this...</span></div>
<div class="line"><a id="l00923" name="l00923"></a><span class="lineno">  923</span>    <span class="comment">// 0x00000004 [2]     C_STEP       (0) Enable single instruction step</span></div>
<div class="line"><a id="l00924" name="l00924"></a><span class="lineno">  924</span>    <span class="comment">// 0x00000002 [1]     C_HALT       (0) PE enter Debug state halt request</span></div>
<div class="line"><a id="l00925" name="l00925"></a><span class="lineno">  925</span>    <span class="comment">// 0x00000001 [0]     C_DEBUGEN    (0) Enable Halting debug</span></div>
<div class="line"><a id="l00926" name="l00926"></a><span class="lineno">  926</span>    io_rw_32 dhcsr;</div>
<div class="line"><a id="l00927" name="l00927"></a><span class="lineno">  927</span> </div>
<div class="line"><a id="l00928" name="l00928"></a><span class="lineno">  928</span>    _REG_(M33_DCRSR_OFFSET) <span class="comment">// M33_DCRSR</span></div>
<div class="line"><a id="l00929" name="l00929"></a><span class="lineno">  929</span>    <span class="comment">// With the DCRDR, provides debug access to the general-purpose registers, special-purpose...</span></div>
<div class="line"><a id="l00930" name="l00930"></a><span class="lineno">  930</span>    <span class="comment">// 0x00010000 [16]    REGWNR       (0) Specifies the access type for the transfer</span></div>
<div class="line"><a id="l00931" name="l00931"></a><span class="lineno">  931</span>    <span class="comment">// 0x0000007f [6:0]   REGSEL       (0x00) Specifies the general-purpose register, special-purpose...</span></div>
<div class="line"><a id="l00932" name="l00932"></a><span class="lineno">  932</span>    io_rw_32 dcrsr;</div>
<div class="line"><a id="l00933" name="l00933"></a><span class="lineno">  933</span> </div>
<div class="line"><a id="l00934" name="l00934"></a><span class="lineno">  934</span>    _REG_(M33_DCRDR_OFFSET) <span class="comment">// M33_DCRDR</span></div>
<div class="line"><a id="l00935" name="l00935"></a><span class="lineno">  935</span>    <span class="comment">// With the DCRSR, provides debug access to the general-purpose registers, special-purpose...</span></div>
<div class="line"><a id="l00936" name="l00936"></a><span class="lineno">  936</span>    <span class="comment">// 0xffffffff [31:0]  DBGTMP       (0x00000000) Provides debug access for reading and writing the...</span></div>
<div class="line"><a id="l00937" name="l00937"></a><span class="lineno">  937</span>    io_rw_32 dcrdr;</div>
<div class="line"><a id="l00938" name="l00938"></a><span class="lineno">  938</span> </div>
<div class="line"><a id="l00939" name="l00939"></a><span class="lineno">  939</span>    _REG_(M33_DEMCR_OFFSET) <span class="comment">// M33_DEMCR</span></div>
<div class="line"><a id="l00940" name="l00940"></a><span class="lineno">  940</span>    <span class="comment">// Manages vector catch behavior and DebugMonitor handling when debugging</span></div>
<div class="line"><a id="l00941" name="l00941"></a><span class="lineno">  941</span>    <span class="comment">// 0x01000000 [24]    TRCENA       (0) Global enable for all DWT and ITM features</span></div>
<div class="line"><a id="l00942" name="l00942"></a><span class="lineno">  942</span>    <span class="comment">// 0x00100000 [20]    SDME         (0) Indicates whether the DebugMonitor targets the Secure or...</span></div>
<div class="line"><a id="l00943" name="l00943"></a><span class="lineno">  943</span>    <span class="comment">// 0x00080000 [19]    MON_REQ      (0) DebugMonitor semaphore bit</span></div>
<div class="line"><a id="l00944" name="l00944"></a><span class="lineno">  944</span>    <span class="comment">// 0x00040000 [18]    MON_STEP     (0) Enable DebugMonitor stepping</span></div>
<div class="line"><a id="l00945" name="l00945"></a><span class="lineno">  945</span>    <span class="comment">// 0x00020000 [17]    MON_PEND     (0) Sets or clears the pending state of the DebugMonitor exception</span></div>
<div class="line"><a id="l00946" name="l00946"></a><span class="lineno">  946</span>    <span class="comment">// 0x00010000 [16]    MON_EN       (0) Enable the DebugMonitor exception</span></div>
<div class="line"><a id="l00947" name="l00947"></a><span class="lineno">  947</span>    <span class="comment">// 0x00000800 [11]    VC_SFERR     (0) SecureFault exception halting debug vector catch enable</span></div>
<div class="line"><a id="l00948" name="l00948"></a><span class="lineno">  948</span>    <span class="comment">// 0x00000400 [10]    VC_HARDERR   (0) HardFault exception halting debug vector catch enable</span></div>
<div class="line"><a id="l00949" name="l00949"></a><span class="lineno">  949</span>    <span class="comment">// 0x00000200 [9]     VC_INTERR    (0) Enable halting debug vector catch for faults during...</span></div>
<div class="line"><a id="l00950" name="l00950"></a><span class="lineno">  950</span>    <span class="comment">// 0x00000100 [8]     VC_BUSERR    (0) BusFault exception halting debug vector catch enable</span></div>
<div class="line"><a id="l00951" name="l00951"></a><span class="lineno">  951</span>    <span class="comment">// 0x00000080 [7]     VC_STATERR   (0) Enable halting debug trap on a UsageFault exception...</span></div>
<div class="line"><a id="l00952" name="l00952"></a><span class="lineno">  952</span>    <span class="comment">// 0x00000040 [6]     VC_CHKERR    (0) Enable halting debug trap on a UsageFault exception...</span></div>
<div class="line"><a id="l00953" name="l00953"></a><span class="lineno">  953</span>    <span class="comment">// 0x00000020 [5]     VC_NOCPERR   (0) Enable halting debug trap on a UsageFault caused by an...</span></div>
<div class="line"><a id="l00954" name="l00954"></a><span class="lineno">  954</span>    <span class="comment">// 0x00000010 [4]     VC_MMERR     (0) Enable halting debug trap on a MemManage exception</span></div>
<div class="line"><a id="l00955" name="l00955"></a><span class="lineno">  955</span>    <span class="comment">// 0x00000001 [0]     VC_CORERESET (0) Enable Reset Vector Catch</span></div>
<div class="line"><a id="l00956" name="l00956"></a><span class="lineno">  956</span>    io_rw_32 demcr;</div>
<div class="line"><a id="l00957" name="l00957"></a><span class="lineno">  957</span> </div>
<div class="line"><a id="l00958" name="l00958"></a><span class="lineno">  958</span>    uint32_t _pad38[2];</div>
<div class="line"><a id="l00959" name="l00959"></a><span class="lineno">  959</span> </div>
<div class="line"><a id="l00960" name="l00960"></a><span class="lineno">  960</span>    _REG_(M33_DSCSR_OFFSET) <span class="comment">// M33_DSCSR</span></div>
<div class="line"><a id="l00961" name="l00961"></a><span class="lineno">  961</span>    <span class="comment">// Provides control and status information for Secure debug</span></div>
<div class="line"><a id="l00962" name="l00962"></a><span class="lineno">  962</span>    <span class="comment">// 0x00020000 [17]    CDSKEY       (0) Writes to the CDS bit are ignored unless CDSKEY is...</span></div>
<div class="line"><a id="l00963" name="l00963"></a><span class="lineno">  963</span>    <span class="comment">// 0x00010000 [16]    CDS          (0) This field indicates the current Security state of the processor</span></div>
<div class="line"><a id="l00964" name="l00964"></a><span class="lineno">  964</span>    <span class="comment">// 0x00000002 [1]     SBRSEL       (0) If SBRSELEN is 1 this bit selects whether the Non-secure...</span></div>
<div class="line"><a id="l00965" name="l00965"></a><span class="lineno">  965</span>    <span class="comment">// 0x00000001 [0]     SBRSELEN     (0) Controls whether the SBRSEL field or the current...</span></div>
<div class="line"><a id="l00966" name="l00966"></a><span class="lineno">  966</span>    io_rw_32 dscsr;</div>
<div class="line"><a id="l00967" name="l00967"></a><span class="lineno">  967</span> </div>
<div class="line"><a id="l00968" name="l00968"></a><span class="lineno">  968</span>    uint32_t _pad39[61];</div>
<div class="line"><a id="l00969" name="l00969"></a><span class="lineno">  969</span> </div>
<div class="line"><a id="l00970" name="l00970"></a><span class="lineno">  970</span>    _REG_(M33_STIR_OFFSET) <span class="comment">// M33_STIR</span></div>
<div class="line"><a id="l00971" name="l00971"></a><span class="lineno">  971</span>    <span class="comment">// Provides a mechanism for software to generate an interrupt</span></div>
<div class="line"><a id="l00972" name="l00972"></a><span class="lineno">  972</span>    <span class="comment">// 0x000001ff [8:0]   INTID        (0x000) Indicates the interrupt to be pended</span></div>
<div class="line"><a id="l00973" name="l00973"></a><span class="lineno">  973</span>    io_rw_32 stir;</div>
<div class="line"><a id="l00974" name="l00974"></a><span class="lineno">  974</span> </div>
<div class="line"><a id="l00975" name="l00975"></a><span class="lineno">  975</span>    uint32_t _pad40[12];</div>
<div class="line"><a id="l00976" name="l00976"></a><span class="lineno">  976</span> </div>
<div class="line"><a id="l00977" name="l00977"></a><span class="lineno">  977</span>    _REG_(M33_FPCCR_OFFSET) <span class="comment">// M33_FPCCR</span></div>
<div class="line"><a id="l00978" name="l00978"></a><span class="lineno">  978</span>    <span class="comment">// Holds control data for the Floating-point extension</span></div>
<div class="line"><a id="l00979" name="l00979"></a><span class="lineno">  979</span>    <span class="comment">// 0x80000000 [31]    ASPEN        (0) When this bit is set to 1, execution of a floating-point...</span></div>
<div class="line"><a id="l00980" name="l00980"></a><span class="lineno">  980</span>    <span class="comment">// 0x40000000 [30]    LSPEN        (0) Enables lazy context save of floating-point state</span></div>
<div class="line"><a id="l00981" name="l00981"></a><span class="lineno">  981</span>    <span class="comment">// 0x20000000 [29]    LSPENS       (1) This bit controls whether the LSPEN bit is writeable...</span></div>
<div class="line"><a id="l00982" name="l00982"></a><span class="lineno">  982</span>    <span class="comment">// 0x10000000 [28]    CLRONRET     (0) Clear floating-point caller saved registers on exception return</span></div>
<div class="line"><a id="l00983" name="l00983"></a><span class="lineno">  983</span>    <span class="comment">// 0x08000000 [27]    CLRONRETS    (0) This bit controls whether the CLRONRET bit is writeable...</span></div>
<div class="line"><a id="l00984" name="l00984"></a><span class="lineno">  984</span>    <span class="comment">// 0x04000000 [26]    TS           (0) Treat floating-point registers as Secure enable</span></div>
<div class="line"><a id="l00985" name="l00985"></a><span class="lineno">  985</span>    <span class="comment">// 0x00000400 [10]    UFRDY        (1) Indicates whether the software executing when the PE...</span></div>
<div class="line"><a id="l00986" name="l00986"></a><span class="lineno">  986</span>    <span class="comment">// 0x00000200 [9]     SPLIMVIOL    (0) This bit is banked between the Security states and...</span></div>
<div class="line"><a id="l00987" name="l00987"></a><span class="lineno">  987</span>    <span class="comment">// 0x00000100 [8]     MONRDY       (0) Indicates whether the software executing when the PE...</span></div>
<div class="line"><a id="l00988" name="l00988"></a><span class="lineno">  988</span>    <span class="comment">// 0x00000080 [7]     SFRDY        (0) Indicates whether the software executing when the PE...</span></div>
<div class="line"><a id="l00989" name="l00989"></a><span class="lineno">  989</span>    <span class="comment">// 0x00000040 [6]     BFRDY        (1) Indicates whether the software executing when the PE...</span></div>
<div class="line"><a id="l00990" name="l00990"></a><span class="lineno">  990</span>    <span class="comment">// 0x00000020 [5]     MMRDY        (1) Indicates whether the software executing when the PE...</span></div>
<div class="line"><a id="l00991" name="l00991"></a><span class="lineno">  991</span>    <span class="comment">// 0x00000010 [4]     HFRDY        (1) Indicates whether the software executing when the PE...</span></div>
<div class="line"><a id="l00992" name="l00992"></a><span class="lineno">  992</span>    <span class="comment">// 0x00000008 [3]     THREAD       (0) Indicates the PE mode when it allocated the...</span></div>
<div class="line"><a id="l00993" name="l00993"></a><span class="lineno">  993</span>    <span class="comment">// 0x00000004 [2]     S            (0) Security status of the floating-point context</span></div>
<div class="line"><a id="l00994" name="l00994"></a><span class="lineno">  994</span>    <span class="comment">// 0x00000002 [1]     USER         (1) Indicates the privilege level of the software executing...</span></div>
<div class="line"><a id="l00995" name="l00995"></a><span class="lineno">  995</span>    <span class="comment">// 0x00000001 [0]     LSPACT       (0) Indicates whether lazy preservation of the...</span></div>
<div class="line"><a id="l00996" name="l00996"></a><span class="lineno">  996</span>    io_rw_32 fpccr;</div>
<div class="line"><a id="l00997" name="l00997"></a><span class="lineno">  997</span> </div>
<div class="line"><a id="l00998" name="l00998"></a><span class="lineno">  998</span>    _REG_(M33_FPCAR_OFFSET) <span class="comment">// M33_FPCAR</span></div>
<div class="line"><a id="l00999" name="l00999"></a><span class="lineno">  999</span>    <span class="comment">// Holds the location of the unpopulated floating-point register space allocated on an exception stack frame</span></div>
<div class="line"><a id="l01000" name="l01000"></a><span class="lineno"> 1000</span>    <span class="comment">// 0xfffffff8 [31:3]  ADDRESS      (0x00000000) The location of the unpopulated floating-point register...</span></div>
<div class="line"><a id="l01001" name="l01001"></a><span class="lineno"> 1001</span>    io_rw_32 fpcar;</div>
<div class="line"><a id="l01002" name="l01002"></a><span class="lineno"> 1002</span> </div>
<div class="line"><a id="l01003" name="l01003"></a><span class="lineno"> 1003</span>    _REG_(M33_FPDSCR_OFFSET) <span class="comment">// M33_FPDSCR</span></div>
<div class="line"><a id="l01004" name="l01004"></a><span class="lineno"> 1004</span>    <span class="comment">// Holds the default values for the floating-point status control data that the PE assigns to the...</span></div>
<div class="line"><a id="l01005" name="l01005"></a><span class="lineno"> 1005</span>    <span class="comment">// 0x04000000 [26]    AHP          (0) Default value for FPSCR</span></div>
<div class="line"><a id="l01006" name="l01006"></a><span class="lineno"> 1006</span>    <span class="comment">// 0x02000000 [25]    DN           (0) Default value for FPSCR</span></div>
<div class="line"><a id="l01007" name="l01007"></a><span class="lineno"> 1007</span>    <span class="comment">// 0x01000000 [24]    FZ           (0) Default value for FPSCR</span></div>
<div class="line"><a id="l01008" name="l01008"></a><span class="lineno"> 1008</span>    <span class="comment">// 0x00c00000 [23:22] RMODE        (0x0) Default value for FPSCR</span></div>
<div class="line"><a id="l01009" name="l01009"></a><span class="lineno"> 1009</span>    io_rw_32 fpdscr;</div>
<div class="line"><a id="l01010" name="l01010"></a><span class="lineno"> 1010</span> </div>
<div class="line"><a id="l01011" name="l01011"></a><span class="lineno"> 1011</span>    <span class="comment">// (Description copied from array index 0 register M33_MVFR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l01012" name="l01012"></a><span class="lineno"> 1012</span>    _REG_(M33_MVFR0_OFFSET) <span class="comment">// M33_MVFR0</span></div>
<div class="line"><a id="l01013" name="l01013"></a><span class="lineno"> 1013</span>    <span class="comment">// Describes the features provided by the Floating-point Extension</span></div>
<div class="line"><a id="l01014" name="l01014"></a><span class="lineno"> 1014</span>    <span class="comment">// 0xf0000000 [31:28] FPROUND      (0x6) Indicates the rounding modes supported by the FP Extension</span></div>
<div class="line"><a id="l01015" name="l01015"></a><span class="lineno"> 1015</span>    <span class="comment">// 0x00f00000 [23:20] FPSQRT       (0x5) Indicates the support for FP square root operations</span></div>
<div class="line"><a id="l01016" name="l01016"></a><span class="lineno"> 1016</span>    <span class="comment">// 0x000f0000 [19:16] FPDIVIDE     (0x4) Indicates the support for FP divide operations</span></div>
<div class="line"><a id="l01017" name="l01017"></a><span class="lineno"> 1017</span>    <span class="comment">// 0x00000f00 [11:8]  FPDP         (0x6) Indicates support for FP double-precision operations</span></div>
<div class="line"><a id="l01018" name="l01018"></a><span class="lineno"> 1018</span>    <span class="comment">// 0x000000f0 [7:4]   FPSP         (0x0) Indicates support for FP single-precision operations</span></div>
<div class="line"><a id="l01019" name="l01019"></a><span class="lineno"> 1019</span>    <span class="comment">// 0x0000000f [3:0]   SIMDREG      (0x1) Indicates size of FP register file</span></div>
<div class="line"><a id="l01020" name="l01020"></a><span class="lineno"> 1020</span>    io_ro_32 mvfr[3];</div>
<div class="line"><a id="l01021" name="l01021"></a><span class="lineno"> 1021</span> </div>
<div class="line"><a id="l01022" name="l01022"></a><span class="lineno"> 1022</span>    uint32_t _pad41[28];</div>
<div class="line"><a id="l01023" name="l01023"></a><span class="lineno"> 1023</span> </div>
<div class="line"><a id="l01024" name="l01024"></a><span class="lineno"> 1024</span>    _REG_(M33_DDEVARCH_OFFSET) <span class="comment">// M33_DDEVARCH</span></div>
<div class="line"><a id="l01025" name="l01025"></a><span class="lineno"> 1025</span>    <span class="comment">// Provides CoreSight discovery information for the SCS</span></div>
<div class="line"><a id="l01026" name="l01026"></a><span class="lineno"> 1026</span>    <span class="comment">// 0xffe00000 [31:21] ARCHITECT    (0x23b) Defines the architect of the component</span></div>
<div class="line"><a id="l01027" name="l01027"></a><span class="lineno"> 1027</span>    <span class="comment">// 0x00100000 [20]    PRESENT      (1) Defines that the DEVARCH register is present</span></div>
<div class="line"><a id="l01028" name="l01028"></a><span class="lineno"> 1028</span>    <span class="comment">// 0x000f0000 [19:16] REVISION     (0x0) Defines the architecture revision of the component</span></div>
<div class="line"><a id="l01029" name="l01029"></a><span class="lineno"> 1029</span>    <span class="comment">// 0x0000f000 [15:12] ARCHVER      (0x2) Defines the architecture version of the component</span></div>
<div class="line"><a id="l01030" name="l01030"></a><span class="lineno"> 1030</span>    <span class="comment">// 0x00000fff [11:0]  ARCHPART     (0xa04) Defines the architecture of the component</span></div>
<div class="line"><a id="l01031" name="l01031"></a><span class="lineno"> 1031</span>    io_ro_32 ddevarch;</div>
<div class="line"><a id="l01032" name="l01032"></a><span class="lineno"> 1032</span> </div>
<div class="line"><a id="l01033" name="l01033"></a><span class="lineno"> 1033</span>    uint32_t _pad42[3];</div>
<div class="line"><a id="l01034" name="l01034"></a><span class="lineno"> 1034</span> </div>
<div class="line"><a id="l01035" name="l01035"></a><span class="lineno"> 1035</span>    _REG_(M33_DDEVTYPE_OFFSET) <span class="comment">// M33_DDEVTYPE</span></div>
<div class="line"><a id="l01036" name="l01036"></a><span class="lineno"> 1036</span>    <span class="comment">// Provides CoreSight discovery information for the SCS</span></div>
<div class="line"><a id="l01037" name="l01037"></a><span class="lineno"> 1037</span>    <span class="comment">// 0x000000f0 [7:4]   SUB          (0x0) Component sub-type</span></div>
<div class="line"><a id="l01038" name="l01038"></a><span class="lineno"> 1038</span>    <span class="comment">// 0x0000000f [3:0]   MAJOR        (0x0) CoreSight major type</span></div>
<div class="line"><a id="l01039" name="l01039"></a><span class="lineno"> 1039</span>    io_ro_32 ddevtype;</div>
<div class="line"><a id="l01040" name="l01040"></a><span class="lineno"> 1040</span> </div>
<div class="line"><a id="l01041" name="l01041"></a><span class="lineno"> 1041</span>    _REG_(M33_DPIDR4_OFFSET) <span class="comment">// M33_DPIDR4</span></div>
<div class="line"><a id="l01042" name="l01042"></a><span class="lineno"> 1042</span>    <span class="comment">// Provides CoreSight discovery information for the SCS</span></div>
<div class="line"><a id="l01043" name="l01043"></a><span class="lineno"> 1043</span>    <span class="comment">// 0x000000f0 [7:4]   SIZE         (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l01044" name="l01044"></a><span class="lineno"> 1044</span>    <span class="comment">// 0x0000000f [3:0]   DES_2        (0x4) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l01045" name="l01045"></a><span class="lineno"> 1045</span>    io_ro_32 dpidr4;</div>
<div class="line"><a id="l01046" name="l01046"></a><span class="lineno"> 1046</span> </div>
<div class="line"><a id="l01047" name="l01047"></a><span class="lineno"> 1047</span>    _REG_(M33_DPIDR5_OFFSET) <span class="comment">// M33_DPIDR5</span></div>
<div class="line"><a id="l01048" name="l01048"></a><span class="lineno"> 1048</span>    <span class="comment">// Provides CoreSight discovery information for the SCS</span></div>
<div class="line"><a id="l01049" name="l01049"></a><span class="lineno"> 1049</span>    <span class="comment">// 0x00000000 [31:0]  DPIDR5       (0x00000000) </span></div>
<div class="line"><a id="l01050" name="l01050"></a><span class="lineno"> 1050</span>    io_rw_32 dpidr5;</div>
<div class="line"><a id="l01051" name="l01051"></a><span class="lineno"> 1051</span> </div>
<div class="line"><a id="l01052" name="l01052"></a><span class="lineno"> 1052</span>    _REG_(M33_DPIDR6_OFFSET) <span class="comment">// M33_DPIDR6</span></div>
<div class="line"><a id="l01053" name="l01053"></a><span class="lineno"> 1053</span>    <span class="comment">// Provides CoreSight discovery information for the SCS</span></div>
<div class="line"><a id="l01054" name="l01054"></a><span class="lineno"> 1054</span>    <span class="comment">// 0x00000000 [31:0]  DPIDR6       (0x00000000) </span></div>
<div class="line"><a id="l01055" name="l01055"></a><span class="lineno"> 1055</span>    io_rw_32 dpidr6;</div>
<div class="line"><a id="l01056" name="l01056"></a><span class="lineno"> 1056</span> </div>
<div class="line"><a id="l01057" name="l01057"></a><span class="lineno"> 1057</span>    _REG_(M33_DPIDR7_OFFSET) <span class="comment">// M33_DPIDR7</span></div>
<div class="line"><a id="l01058" name="l01058"></a><span class="lineno"> 1058</span>    <span class="comment">// Provides CoreSight discovery information for the SCS</span></div>
<div class="line"><a id="l01059" name="l01059"></a><span class="lineno"> 1059</span>    <span class="comment">// 0x00000000 [31:0]  DPIDR7       (0x00000000) </span></div>
<div class="line"><a id="l01060" name="l01060"></a><span class="lineno"> 1060</span>    io_rw_32 dpidr7;</div>
<div class="line"><a id="l01061" name="l01061"></a><span class="lineno"> 1061</span> </div>
<div class="line"><a id="l01062" name="l01062"></a><span class="lineno"> 1062</span>    _REG_(M33_DPIDR0_OFFSET) <span class="comment">// M33_DPIDR0</span></div>
<div class="line"><a id="l01063" name="l01063"></a><span class="lineno"> 1063</span>    <span class="comment">// Provides CoreSight discovery information for the SCS</span></div>
<div class="line"><a id="l01064" name="l01064"></a><span class="lineno"> 1064</span>    <span class="comment">// 0x000000ff [7:0]   PART_0       (0x21) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l01065" name="l01065"></a><span class="lineno"> 1065</span>    io_ro_32 dpidr0;</div>
<div class="line"><a id="l01066" name="l01066"></a><span class="lineno"> 1066</span> </div>
<div class="line"><a id="l01067" name="l01067"></a><span class="lineno"> 1067</span>    _REG_(M33_DPIDR1_OFFSET) <span class="comment">// M33_DPIDR1</span></div>
<div class="line"><a id="l01068" name="l01068"></a><span class="lineno"> 1068</span>    <span class="comment">// Provides CoreSight discovery information for the SCS</span></div>
<div class="line"><a id="l01069" name="l01069"></a><span class="lineno"> 1069</span>    <span class="comment">// 0x000000f0 [7:4]   DES_0        (0xb) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l01070" name="l01070"></a><span class="lineno"> 1070</span>    <span class="comment">// 0x0000000f [3:0]   PART_1       (0xd) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l01071" name="l01071"></a><span class="lineno"> 1071</span>    io_ro_32 dpidr1;</div>
<div class="line"><a id="l01072" name="l01072"></a><span class="lineno"> 1072</span> </div>
<div class="line"><a id="l01073" name="l01073"></a><span class="lineno"> 1073</span>    _REG_(M33_DPIDR2_OFFSET) <span class="comment">// M33_DPIDR2</span></div>
<div class="line"><a id="l01074" name="l01074"></a><span class="lineno"> 1074</span>    <span class="comment">// Provides CoreSight discovery information for the SCS</span></div>
<div class="line"><a id="l01075" name="l01075"></a><span class="lineno"> 1075</span>    <span class="comment">// 0x000000f0 [7:4]   REVISION     (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l01076" name="l01076"></a><span class="lineno"> 1076</span>    <span class="comment">// 0x00000008 [3]     JEDEC        (1) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l01077" name="l01077"></a><span class="lineno"> 1077</span>    <span class="comment">// 0x00000007 [2:0]   DES_1        (0x3) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l01078" name="l01078"></a><span class="lineno"> 1078</span>    io_ro_32 dpidr2;</div>
<div class="line"><a id="l01079" name="l01079"></a><span class="lineno"> 1079</span> </div>
<div class="line"><a id="l01080" name="l01080"></a><span class="lineno"> 1080</span>    _REG_(M33_DPIDR3_OFFSET) <span class="comment">// M33_DPIDR3</span></div>
<div class="line"><a id="l01081" name="l01081"></a><span class="lineno"> 1081</span>    <span class="comment">// Provides CoreSight discovery information for the SCS</span></div>
<div class="line"><a id="l01082" name="l01082"></a><span class="lineno"> 1082</span>    <span class="comment">// 0x000000f0 [7:4]   REVAND       (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l01083" name="l01083"></a><span class="lineno"> 1083</span>    <span class="comment">// 0x0000000f [3:0]   CMOD         (0x0) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l01084" name="l01084"></a><span class="lineno"> 1084</span>    io_ro_32 dpidr3;</div>
<div class="line"><a id="l01085" name="l01085"></a><span class="lineno"> 1085</span> </div>
<div class="line"><a id="l01086" name="l01086"></a><span class="lineno"> 1086</span>    <span class="comment">// (Description copied from array index 0 register M33_DCIDR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l01087" name="l01087"></a><span class="lineno"> 1087</span>    _REG_(M33_DCIDR0_OFFSET) <span class="comment">// M33_DCIDR0</span></div>
<div class="line"><a id="l01088" name="l01088"></a><span class="lineno"> 1088</span>    <span class="comment">// Provides CoreSight discovery information for the SCS</span></div>
<div class="line"><a id="l01089" name="l01089"></a><span class="lineno"> 1089</span>    <span class="comment">// 0x000000ff [7:0]   PRMBL_0      (0x0d) See CoreSight Architecture Specification</span></div>
<div class="line"><a id="l01090" name="l01090"></a><span class="lineno"> 1090</span>    io_ro_32 dcidr[4];</div>
<div class="line"><a id="l01091" name="l01091"></a><span class="lineno"> 1091</span> </div>
<div class="line"><a id="l01092" name="l01092"></a><span class="lineno"> 1092</span>    uint32_t _pad43[51201];</div>
<div class="line"><a id="l01093" name="l01093"></a><span class="lineno"> 1093</span> </div>
<div class="line"><a id="l01094" name="l01094"></a><span class="lineno"> 1094</span>    _REG_(M33_TRCPRGCTLR_OFFSET) <span class="comment">// M33_TRCPRGCTLR</span></div>
<div class="line"><a id="l01095" name="l01095"></a><span class="lineno"> 1095</span>    <span class="comment">// Programming Control Register</span></div>
<div class="line"><a id="l01096" name="l01096"></a><span class="lineno"> 1096</span>    <span class="comment">// 0x00000001 [0]     EN           (0) Trace Unit Enable</span></div>
<div class="line"><a id="l01097" name="l01097"></a><span class="lineno"> 1097</span>    io_rw_32 trcprgctlr;</div>
<div class="line"><a id="l01098" name="l01098"></a><span class="lineno"> 1098</span> </div>
<div class="line"><a id="l01099" name="l01099"></a><span class="lineno"> 1099</span>    uint32_t _pad44;</div>
<div class="line"><a id="l01100" name="l01100"></a><span class="lineno"> 1100</span> </div>
<div class="line"><a id="l01101" name="l01101"></a><span class="lineno"> 1101</span>    _REG_(M33_TRCSTATR_OFFSET) <span class="comment">// M33_TRCSTATR</span></div>
<div class="line"><a id="l01102" name="l01102"></a><span class="lineno"> 1102</span>    <span class="comment">// The TRCSTATR indicates the ETM-Teal status</span></div>
<div class="line"><a id="l01103" name="l01103"></a><span class="lineno"> 1103</span>    <span class="comment">// 0x00000002 [1]     PMSTABLE     (0) Indicates whether the ETM-Teal registers are stable and...</span></div>
<div class="line"><a id="l01104" name="l01104"></a><span class="lineno"> 1104</span>    <span class="comment">// 0x00000001 [0]     IDLE         (0) Indicates that the trace unit is inactive</span></div>
<div class="line"><a id="l01105" name="l01105"></a><span class="lineno"> 1105</span>    io_ro_32 trcstatr;</div>
<div class="line"><a id="l01106" name="l01106"></a><span class="lineno"> 1106</span> </div>
<div class="line"><a id="l01107" name="l01107"></a><span class="lineno"> 1107</span>    _REG_(M33_TRCCONFIGR_OFFSET) <span class="comment">// M33_TRCCONFIGR</span></div>
<div class="line"><a id="l01108" name="l01108"></a><span class="lineno"> 1108</span>    <span class="comment">// The TRCCONFIGR sets the basic tracing options for the trace unit</span></div>
<div class="line"><a id="l01109" name="l01109"></a><span class="lineno"> 1109</span>    <span class="comment">// 0x00001000 [12]    RS           (0) Return stack enable</span></div>
<div class="line"><a id="l01110" name="l01110"></a><span class="lineno"> 1110</span>    <span class="comment">// 0x00000800 [11]    TS           (0) Global timestamp tracing</span></div>
<div class="line"><a id="l01111" name="l01111"></a><span class="lineno"> 1111</span>    <span class="comment">// 0x000007e0 [10:5]  COND         (0x00) Conditional instruction tracing</span></div>
<div class="line"><a id="l01112" name="l01112"></a><span class="lineno"> 1112</span>    <span class="comment">// 0x00000010 [4]     CCI          (0) Cycle counting in instruction trace</span></div>
<div class="line"><a id="l01113" name="l01113"></a><span class="lineno"> 1113</span>    <span class="comment">// 0x00000008 [3]     BB           (0) Branch broadcast mode</span></div>
<div class="line"><a id="l01114" name="l01114"></a><span class="lineno"> 1114</span>    io_rw_32 trcconfigr;</div>
<div class="line"><a id="l01115" name="l01115"></a><span class="lineno"> 1115</span> </div>
<div class="line"><a id="l01116" name="l01116"></a><span class="lineno"> 1116</span>    uint32_t _pad45[3];</div>
<div class="line"><a id="l01117" name="l01117"></a><span class="lineno"> 1117</span> </div>
<div class="line"><a id="l01118" name="l01118"></a><span class="lineno"> 1118</span>    _REG_(M33_TRCEVENTCTL0R_OFFSET) <span class="comment">// M33_TRCEVENTCTL0R</span></div>
<div class="line"><a id="l01119" name="l01119"></a><span class="lineno"> 1119</span>    <span class="comment">// The TRCEVENTCTL0R controls the tracing of events in the trace stream</span></div>
<div class="line"><a id="l01120" name="l01120"></a><span class="lineno"> 1120</span>    <span class="comment">// 0x00008000 [15]    TYPE1        (0) Selects the resource type for event 1</span></div>
<div class="line"><a id="l01121" name="l01121"></a><span class="lineno"> 1121</span>    <span class="comment">// 0x00000700 [10:8]  SEL1         (0x0) Selects the resource number, based on the value of...</span></div>
<div class="line"><a id="l01122" name="l01122"></a><span class="lineno"> 1122</span>    <span class="comment">// 0x00000080 [7]     TYPE0        (0) Selects the resource type for event 0</span></div>
<div class="line"><a id="l01123" name="l01123"></a><span class="lineno"> 1123</span>    <span class="comment">// 0x00000007 [2:0]   SEL0         (0x0) Selects the resource number, based on the value of...</span></div>
<div class="line"><a id="l01124" name="l01124"></a><span class="lineno"> 1124</span>    io_rw_32 trceventctl0r;</div>
<div class="line"><a id="l01125" name="l01125"></a><span class="lineno"> 1125</span> </div>
<div class="line"><a id="l01126" name="l01126"></a><span class="lineno"> 1126</span>    _REG_(M33_TRCEVENTCTL1R_OFFSET) <span class="comment">// M33_TRCEVENTCTL1R</span></div>
<div class="line"><a id="l01127" name="l01127"></a><span class="lineno"> 1127</span>    <span class="comment">// The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave</span></div>
<div class="line"><a id="l01128" name="l01128"></a><span class="lineno"> 1128</span>    <span class="comment">// 0x00001000 [12]    LPOVERRIDE   (0) Low power state behavior override</span></div>
<div class="line"><a id="l01129" name="l01129"></a><span class="lineno"> 1129</span>    <span class="comment">// 0x00000800 [11]    ATB          (0) ATB enabled</span></div>
<div class="line"><a id="l01130" name="l01130"></a><span class="lineno"> 1130</span>    <span class="comment">// 0x00000002 [1]     INSTEN1      (0) One bit per event, to enable generation of an event...</span></div>
<div class="line"><a id="l01131" name="l01131"></a><span class="lineno"> 1131</span>    <span class="comment">// 0x00000001 [0]     INSTEN0      (0) One bit per event, to enable generation of an event...</span></div>
<div class="line"><a id="l01132" name="l01132"></a><span class="lineno"> 1132</span>    io_rw_32 trceventctl1r;</div>
<div class="line"><a id="l01133" name="l01133"></a><span class="lineno"> 1133</span> </div>
<div class="line"><a id="l01134" name="l01134"></a><span class="lineno"> 1134</span>    uint32_t _pad46;</div>
<div class="line"><a id="l01135" name="l01135"></a><span class="lineno"> 1135</span> </div>
<div class="line"><a id="l01136" name="l01136"></a><span class="lineno"> 1136</span>    _REG_(M33_TRCSTALLCTLR_OFFSET) <span class="comment">// M33_TRCSTALLCTLR</span></div>
<div class="line"><a id="l01137" name="l01137"></a><span class="lineno"> 1137</span>    <span class="comment">// The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the...</span></div>
<div class="line"><a id="l01138" name="l01138"></a><span class="lineno"> 1138</span>    <span class="comment">// 0x00000400 [10]    INSTPRIORITY (0) Reserved, RES0</span></div>
<div class="line"><a id="l01139" name="l01139"></a><span class="lineno"> 1139</span>    <span class="comment">// 0x00000100 [8]     ISTALL       (0) Stall processor based on instruction trace buffer space</span></div>
<div class="line"><a id="l01140" name="l01140"></a><span class="lineno"> 1140</span>    <span class="comment">// 0x0000000c [3:2]   LEVEL        (0x0) Threshold at which stalling becomes active</span></div>
<div class="line"><a id="l01141" name="l01141"></a><span class="lineno"> 1141</span>    io_rw_32 trcstallctlr;</div>
<div class="line"><a id="l01142" name="l01142"></a><span class="lineno"> 1142</span> </div>
<div class="line"><a id="l01143" name="l01143"></a><span class="lineno"> 1143</span>    _REG_(M33_TRCTSCTLR_OFFSET) <span class="comment">// M33_TRCTSCTLR</span></div>
<div class="line"><a id="l01144" name="l01144"></a><span class="lineno"> 1144</span>    <span class="comment">// The TRCTSCTLR controls the insertion of global timestamps into the trace stream</span></div>
<div class="line"><a id="l01145" name="l01145"></a><span class="lineno"> 1145</span>    <span class="comment">// 0x00000080 [7]     TYPE0        (0) Selects the resource type for event 0</span></div>
<div class="line"><a id="l01146" name="l01146"></a><span class="lineno"> 1146</span>    <span class="comment">// 0x00000003 [1:0]   SEL0         (0x0) Selects the resource number, based on the value of...</span></div>
<div class="line"><a id="l01147" name="l01147"></a><span class="lineno"> 1147</span>    io_rw_32 trctsctlr;</div>
<div class="line"><a id="l01148" name="l01148"></a><span class="lineno"> 1148</span> </div>
<div class="line"><a id="l01149" name="l01149"></a><span class="lineno"> 1149</span>    _REG_(M33_TRCSYNCPR_OFFSET) <span class="comment">// M33_TRCSYNCPR</span></div>
<div class="line"><a id="l01150" name="l01150"></a><span class="lineno"> 1150</span>    <span class="comment">// The TRCSYNCPR specifies the period of trace synchronization of the trace streams</span></div>
<div class="line"><a id="l01151" name="l01151"></a><span class="lineno"> 1151</span>    <span class="comment">// 0x0000001f [4:0]   PERIOD       (0x0a) Defines the number of bytes of trace between trace...</span></div>
<div class="line"><a id="l01152" name="l01152"></a><span class="lineno"> 1152</span>    io_ro_32 trcsyncpr;</div>
<div class="line"><a id="l01153" name="l01153"></a><span class="lineno"> 1153</span> </div>
<div class="line"><a id="l01154" name="l01154"></a><span class="lineno"> 1154</span>    _REG_(M33_TRCCCCTLR_OFFSET) <span class="comment">// M33_TRCCCCTLR</span></div>
<div class="line"><a id="l01155" name="l01155"></a><span class="lineno"> 1155</span>    <span class="comment">// The TRCCCCTLR sets the threshold value for instruction trace cycle counting</span></div>
<div class="line"><a id="l01156" name="l01156"></a><span class="lineno"> 1156</span>    <span class="comment">// 0x00000fff [11:0]  THRESHOLD    (0x000) Instruction trace cycle count threshold</span></div>
<div class="line"><a id="l01157" name="l01157"></a><span class="lineno"> 1157</span>    io_rw_32 trcccctlr;</div>
<div class="line"><a id="l01158" name="l01158"></a><span class="lineno"> 1158</span> </div>
<div class="line"><a id="l01159" name="l01159"></a><span class="lineno"> 1159</span>    uint32_t _pad47[17];</div>
<div class="line"><a id="l01160" name="l01160"></a><span class="lineno"> 1160</span> </div>
<div class="line"><a id="l01161" name="l01161"></a><span class="lineno"> 1161</span>    _REG_(M33_TRCVICTLR_OFFSET) <span class="comment">// M33_TRCVICTLR</span></div>
<div class="line"><a id="l01162" name="l01162"></a><span class="lineno"> 1162</span>    <span class="comment">// The TRCVICTLR controls instruction trace filtering</span></div>
<div class="line"><a id="l01163" name="l01163"></a><span class="lineno"> 1163</span>    <span class="comment">// 0x00080000 [19]    EXLEVEL_S3   (0) In Secure state, each bit controls whether instruction...</span></div>
<div class="line"><a id="l01164" name="l01164"></a><span class="lineno"> 1164</span>    <span class="comment">// 0x00010000 [16]    EXLEVEL_S0   (0) In Secure state, each bit controls whether instruction...</span></div>
<div class="line"><a id="l01165" name="l01165"></a><span class="lineno"> 1165</span>    <span class="comment">// 0x00000800 [11]    TRCERR       (0) Selects whether a system error exception must always be traced</span></div>
<div class="line"><a id="l01166" name="l01166"></a><span class="lineno"> 1166</span>    <span class="comment">// 0x00000400 [10]    TRCRESET     (0) Selects whether a reset exception must always be traced</span></div>
<div class="line"><a id="l01167" name="l01167"></a><span class="lineno"> 1167</span>    <span class="comment">// 0x00000200 [9]     SSSTATUS     (0) Indicates the current status of the start/stop logic</span></div>
<div class="line"><a id="l01168" name="l01168"></a><span class="lineno"> 1168</span>    <span class="comment">// 0x00000080 [7]     TYPE0        (0) Selects the resource type for event 0</span></div>
<div class="line"><a id="l01169" name="l01169"></a><span class="lineno"> 1169</span>    <span class="comment">// 0x00000003 [1:0]   SEL0         (0x0) Selects the resource number, based on the value of...</span></div>
<div class="line"><a id="l01170" name="l01170"></a><span class="lineno"> 1170</span>    io_rw_32 trcvictlr;</div>
<div class="line"><a id="l01171" name="l01171"></a><span class="lineno"> 1171</span> </div>
<div class="line"><a id="l01172" name="l01172"></a><span class="lineno"> 1172</span>    uint32_t _pad48[47];</div>
<div class="line"><a id="l01173" name="l01173"></a><span class="lineno"> 1173</span> </div>
<div class="line"><a id="l01174" name="l01174"></a><span class="lineno"> 1174</span>    _REG_(M33_TRCCNTRLDVR0_OFFSET) <span class="comment">// M33_TRCCNTRLDVR0</span></div>
<div class="line"><a id="l01175" name="l01175"></a><span class="lineno"> 1175</span>    <span class="comment">// The TRCCNTRLDVR defines the reload value for the reduced function counter</span></div>
<div class="line"><a id="l01176" name="l01176"></a><span class="lineno"> 1176</span>    <span class="comment">// 0x0000ffff [15:0]  VALUE        (0x0000) Defines the reload value for the counter</span></div>
<div class="line"><a id="l01177" name="l01177"></a><span class="lineno"> 1177</span>    io_rw_32 trccntrldvr0;</div>
<div class="line"><a id="l01178" name="l01178"></a><span class="lineno"> 1178</span> </div>
<div class="line"><a id="l01179" name="l01179"></a><span class="lineno"> 1179</span>    uint32_t _pad49[15];</div>
<div class="line"><a id="l01180" name="l01180"></a><span class="lineno"> 1180</span> </div>
<div class="line"><a id="l01181" name="l01181"></a><span class="lineno"> 1181</span>    _REG_(M33_TRCIDR8_OFFSET) <span class="comment">// M33_TRCIDR8</span></div>
<div class="line"><a id="l01182" name="l01182"></a><span class="lineno"> 1182</span>    <span class="comment">// TRCIDR8</span></div>
<div class="line"><a id="l01183" name="l01183"></a><span class="lineno"> 1183</span>    <span class="comment">// 0xffffffff [31:0]  MAXSPEC      (0x00000000) reads as `ImpDef</span></div>
<div class="line"><a id="l01184" name="l01184"></a><span class="lineno"> 1184</span>    io_ro_32 trcidr8;</div>
<div class="line"><a id="l01185" name="l01185"></a><span class="lineno"> 1185</span> </div>
<div class="line"><a id="l01186" name="l01186"></a><span class="lineno"> 1186</span>    _REG_(M33_TRCIDR9_OFFSET) <span class="comment">// M33_TRCIDR9</span></div>
<div class="line"><a id="l01187" name="l01187"></a><span class="lineno"> 1187</span>    <span class="comment">// TRCIDR9</span></div>
<div class="line"><a id="l01188" name="l01188"></a><span class="lineno"> 1188</span>    <span class="comment">// 0xffffffff [31:0]  NUMP0KEY     (0x00000000) reads as `ImpDef</span></div>
<div class="line"><a id="l01189" name="l01189"></a><span class="lineno"> 1189</span>    io_ro_32 trcidr9;</div>
<div class="line"><a id="l01190" name="l01190"></a><span class="lineno"> 1190</span> </div>
<div class="line"><a id="l01191" name="l01191"></a><span class="lineno"> 1191</span>    _REG_(M33_TRCIDR10_OFFSET) <span class="comment">// M33_TRCIDR10</span></div>
<div class="line"><a id="l01192" name="l01192"></a><span class="lineno"> 1192</span>    <span class="comment">// TRCIDR10</span></div>
<div class="line"><a id="l01193" name="l01193"></a><span class="lineno"> 1193</span>    <span class="comment">// 0xffffffff [31:0]  NUMP1KEY     (0x00000000) reads as `ImpDef</span></div>
<div class="line"><a id="l01194" name="l01194"></a><span class="lineno"> 1194</span>    io_ro_32 trcidr10;</div>
<div class="line"><a id="l01195" name="l01195"></a><span class="lineno"> 1195</span> </div>
<div class="line"><a id="l01196" name="l01196"></a><span class="lineno"> 1196</span>    _REG_(M33_TRCIDR11_OFFSET) <span class="comment">// M33_TRCIDR11</span></div>
<div class="line"><a id="l01197" name="l01197"></a><span class="lineno"> 1197</span>    <span class="comment">// TRCIDR11</span></div>
<div class="line"><a id="l01198" name="l01198"></a><span class="lineno"> 1198</span>    <span class="comment">// 0xffffffff [31:0]  NUMP1SPC     (0x00000000) reads as `ImpDef</span></div>
<div class="line"><a id="l01199" name="l01199"></a><span class="lineno"> 1199</span>    io_ro_32 trcidr11;</div>
<div class="line"><a id="l01200" name="l01200"></a><span class="lineno"> 1200</span> </div>
<div class="line"><a id="l01201" name="l01201"></a><span class="lineno"> 1201</span>    _REG_(M33_TRCIDR12_OFFSET) <span class="comment">// M33_TRCIDR12</span></div>
<div class="line"><a id="l01202" name="l01202"></a><span class="lineno"> 1202</span>    <span class="comment">// TRCIDR12</span></div>
<div class="line"><a id="l01203" name="l01203"></a><span class="lineno"> 1203</span>    <span class="comment">// 0xffffffff [31:0]  NUMCONDKEY   (0x00000001) reads as `ImpDef</span></div>
<div class="line"><a id="l01204" name="l01204"></a><span class="lineno"> 1204</span>    io_ro_32 trcidr12;</div>
<div class="line"><a id="l01205" name="l01205"></a><span class="lineno"> 1205</span> </div>
<div class="line"><a id="l01206" name="l01206"></a><span class="lineno"> 1206</span>    _REG_(M33_TRCIDR13_OFFSET) <span class="comment">// M33_TRCIDR13</span></div>
<div class="line"><a id="l01207" name="l01207"></a><span class="lineno"> 1207</span>    <span class="comment">// TRCIDR13</span></div>
<div class="line"><a id="l01208" name="l01208"></a><span class="lineno"> 1208</span>    <span class="comment">// 0xffffffff [31:0]  NUMCONDSPC   (0x00000000) reads as `ImpDef</span></div>
<div class="line"><a id="l01209" name="l01209"></a><span class="lineno"> 1209</span>    io_ro_32 trcidr13;</div>
<div class="line"><a id="l01210" name="l01210"></a><span class="lineno"> 1210</span> </div>
<div class="line"><a id="l01211" name="l01211"></a><span class="lineno"> 1211</span>    uint32_t _pad50[10];</div>
<div class="line"><a id="l01212" name="l01212"></a><span class="lineno"> 1212</span> </div>
<div class="line"><a id="l01213" name="l01213"></a><span class="lineno"> 1213</span>    _REG_(M33_TRCIMSPEC_OFFSET) <span class="comment">// M33_TRCIMSPEC</span></div>
<div class="line"><a id="l01214" name="l01214"></a><span class="lineno"> 1214</span>    <span class="comment">// The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any...</span></div>
<div class="line"><a id="l01215" name="l01215"></a><span class="lineno"> 1215</span>    <span class="comment">// 0x0000000f [3:0]   SUPPORT      (0x0) Reserved, RES0</span></div>
<div class="line"><a id="l01216" name="l01216"></a><span class="lineno"> 1216</span>    io_ro_32 trcimspec;</div>
<div class="line"><a id="l01217" name="l01217"></a><span class="lineno"> 1217</span> </div>
<div class="line"><a id="l01218" name="l01218"></a><span class="lineno"> 1218</span>    uint32_t _pad51[7];</div>
<div class="line"><a id="l01219" name="l01219"></a><span class="lineno"> 1219</span> </div>
<div class="line"><a id="l01220" name="l01220"></a><span class="lineno"> 1220</span>    _REG_(M33_TRCIDR0_OFFSET) <span class="comment">// M33_TRCIDR0</span></div>
<div class="line"><a id="l01221" name="l01221"></a><span class="lineno"> 1221</span>    <span class="comment">// TRCIDR0</span></div>
<div class="line"><a id="l01222" name="l01222"></a><span class="lineno"> 1222</span>    <span class="comment">// 0x20000000 [29]    COMMOPT      (1) reads as `ImpDef</span></div>
<div class="line"><a id="l01223" name="l01223"></a><span class="lineno"> 1223</span>    <span class="comment">// 0x1f000000 [28:24] TSSIZE       (0x08) reads as `ImpDef</span></div>
<div class="line"><a id="l01224" name="l01224"></a><span class="lineno"> 1224</span>    <span class="comment">// 0x00020000 [17]    TRCEXDATA    (0) reads as `ImpDef</span></div>
<div class="line"><a id="l01225" name="l01225"></a><span class="lineno"> 1225</span>    <span class="comment">// 0x00018000 [16:15] QSUPP        (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01226" name="l01226"></a><span class="lineno"> 1226</span>    <span class="comment">// 0x00004000 [14]    QFILT        (0) reads as `ImpDef</span></div>
<div class="line"><a id="l01227" name="l01227"></a><span class="lineno"> 1227</span>    <span class="comment">// 0x00003000 [13:12] CONDTYPE     (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01228" name="l01228"></a><span class="lineno"> 1228</span>    <span class="comment">// 0x00000c00 [11:10] NUMEVENT     (0x1) reads as `ImpDef</span></div>
<div class="line"><a id="l01229" name="l01229"></a><span class="lineno"> 1229</span>    <span class="comment">// 0x00000200 [9]     RETSTACK     (1) reads as `ImpDef</span></div>
<div class="line"><a id="l01230" name="l01230"></a><span class="lineno"> 1230</span>    <span class="comment">// 0x00000080 [7]     TRCCCI       (1) reads as `ImpDef</span></div>
<div class="line"><a id="l01231" name="l01231"></a><span class="lineno"> 1231</span>    <span class="comment">// 0x00000040 [6]     TRCCOND      (1) reads as `ImpDef</span></div>
<div class="line"><a id="l01232" name="l01232"></a><span class="lineno"> 1232</span>    <span class="comment">// 0x00000020 [5]     TRCBB        (1) reads as `ImpDef</span></div>
<div class="line"><a id="l01233" name="l01233"></a><span class="lineno"> 1233</span>    <span class="comment">// 0x00000018 [4:3]   TRCDATA      (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01234" name="l01234"></a><span class="lineno"> 1234</span>    <span class="comment">// 0x00000006 [2:1]   INSTP0       (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01235" name="l01235"></a><span class="lineno"> 1235</span>    <span class="comment">// 0x00000001 [0]     RES1         (1) Reserved, RES1</span></div>
<div class="line"><a id="l01236" name="l01236"></a><span class="lineno"> 1236</span>    io_ro_32 trcidr0;</div>
<div class="line"><a id="l01237" name="l01237"></a><span class="lineno"> 1237</span> </div>
<div class="line"><a id="l01238" name="l01238"></a><span class="lineno"> 1238</span>    _REG_(M33_TRCIDR1_OFFSET) <span class="comment">// M33_TRCIDR1</span></div>
<div class="line"><a id="l01239" name="l01239"></a><span class="lineno"> 1239</span>    <span class="comment">// TRCIDR1</span></div>
<div class="line"><a id="l01240" name="l01240"></a><span class="lineno"> 1240</span>    <span class="comment">// 0xff000000 [31:24] DESIGNER     (0x41) reads as `ImpDef</span></div>
<div class="line"><a id="l01241" name="l01241"></a><span class="lineno"> 1241</span>    <span class="comment">// 0x0000f000 [15:12] RES1         (0xf) Reserved, RES1</span></div>
<div class="line"><a id="l01242" name="l01242"></a><span class="lineno"> 1242</span>    <span class="comment">// 0x00000f00 [11:8]  TRCARCHMAJ   (0x4) reads as 0b0100</span></div>
<div class="line"><a id="l01243" name="l01243"></a><span class="lineno"> 1243</span>    <span class="comment">// 0x000000f0 [7:4]   TRCARCHMIN   (0x2) reads as 0b0000</span></div>
<div class="line"><a id="l01244" name="l01244"></a><span class="lineno"> 1244</span>    <span class="comment">// 0x0000000f [3:0]   REVISION     (0x1) reads as `ImpDef</span></div>
<div class="line"><a id="l01245" name="l01245"></a><span class="lineno"> 1245</span>    io_ro_32 trcidr1;</div>
<div class="line"><a id="l01246" name="l01246"></a><span class="lineno"> 1246</span> </div>
<div class="line"><a id="l01247" name="l01247"></a><span class="lineno"> 1247</span>    _REG_(M33_TRCIDR2_OFFSET) <span class="comment">// M33_TRCIDR2</span></div>
<div class="line"><a id="l01248" name="l01248"></a><span class="lineno"> 1248</span>    <span class="comment">// TRCIDR2</span></div>
<div class="line"><a id="l01249" name="l01249"></a><span class="lineno"> 1249</span>    <span class="comment">// 0x1e000000 [28:25] CCSIZE       (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01250" name="l01250"></a><span class="lineno"> 1250</span>    <span class="comment">// 0x01f00000 [24:20] DVSIZE       (0x00) reads as `ImpDef</span></div>
<div class="line"><a id="l01251" name="l01251"></a><span class="lineno"> 1251</span>    <span class="comment">// 0x000f8000 [19:15] DASIZE       (0x00) reads as `ImpDef</span></div>
<div class="line"><a id="l01252" name="l01252"></a><span class="lineno"> 1252</span>    <span class="comment">// 0x00007c00 [14:10] VMIDSIZE     (0x00) reads as `ImpDef</span></div>
<div class="line"><a id="l01253" name="l01253"></a><span class="lineno"> 1253</span>    <span class="comment">// 0x000003e0 [9:5]   CIDSIZE      (0x00) reads as `ImpDef</span></div>
<div class="line"><a id="l01254" name="l01254"></a><span class="lineno"> 1254</span>    <span class="comment">// 0x0000001f [4:0]   IASIZE       (0x04) reads as `ImpDef</span></div>
<div class="line"><a id="l01255" name="l01255"></a><span class="lineno"> 1255</span>    io_ro_32 trcidr2;</div>
<div class="line"><a id="l01256" name="l01256"></a><span class="lineno"> 1256</span> </div>
<div class="line"><a id="l01257" name="l01257"></a><span class="lineno"> 1257</span>    _REG_(M33_TRCIDR3_OFFSET) <span class="comment">// M33_TRCIDR3</span></div>
<div class="line"><a id="l01258" name="l01258"></a><span class="lineno"> 1258</span>    <span class="comment">// TRCIDR3</span></div>
<div class="line"><a id="l01259" name="l01259"></a><span class="lineno"> 1259</span>    <span class="comment">// 0x80000000 [31]    NOOVERFLOW   (0) reads as `ImpDef</span></div>
<div class="line"><a id="l01260" name="l01260"></a><span class="lineno"> 1260</span>    <span class="comment">// 0x70000000 [30:28] NUMPROC      (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01261" name="l01261"></a><span class="lineno"> 1261</span>    <span class="comment">// 0x08000000 [27]    SYSSTALL     (1) reads as `ImpDef</span></div>
<div class="line"><a id="l01262" name="l01262"></a><span class="lineno"> 1262</span>    <span class="comment">// 0x04000000 [26]    STALLCTL     (1) reads as `ImpDef</span></div>
<div class="line"><a id="l01263" name="l01263"></a><span class="lineno"> 1263</span>    <span class="comment">// 0x02000000 [25]    SYNCPR       (1) reads as `ImpDef</span></div>
<div class="line"><a id="l01264" name="l01264"></a><span class="lineno"> 1264</span>    <span class="comment">// 0x01000000 [24]    TRCERR       (1) reads as `ImpDef</span></div>
<div class="line"><a id="l01265" name="l01265"></a><span class="lineno"> 1265</span>    <span class="comment">// 0x00f00000 [23:20] EXLEVEL_NS   (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01266" name="l01266"></a><span class="lineno"> 1266</span>    <span class="comment">// 0x000f0000 [19:16] EXLEVEL_S    (0x9) reads as `ImpDef</span></div>
<div class="line"><a id="l01267" name="l01267"></a><span class="lineno"> 1267</span>    <span class="comment">// 0x00000fff [11:0]  CCITMIN      (0x004) reads as `ImpDef</span></div>
<div class="line"><a id="l01268" name="l01268"></a><span class="lineno"> 1268</span>    io_ro_32 trcidr3;</div>
<div class="line"><a id="l01269" name="l01269"></a><span class="lineno"> 1269</span> </div>
<div class="line"><a id="l01270" name="l01270"></a><span class="lineno"> 1270</span>    _REG_(M33_TRCIDR4_OFFSET) <span class="comment">// M33_TRCIDR4</span></div>
<div class="line"><a id="l01271" name="l01271"></a><span class="lineno"> 1271</span>    <span class="comment">// TRCIDR4</span></div>
<div class="line"><a id="l01272" name="l01272"></a><span class="lineno"> 1272</span>    <span class="comment">// 0xf0000000 [31:28] NUMVMIDC     (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01273" name="l01273"></a><span class="lineno"> 1273</span>    <span class="comment">// 0x0f000000 [27:24] NUMCIDC      (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01274" name="l01274"></a><span class="lineno"> 1274</span>    <span class="comment">// 0x00f00000 [23:20] NUMSSCC      (0x1) reads as `ImpDef</span></div>
<div class="line"><a id="l01275" name="l01275"></a><span class="lineno"> 1275</span>    <span class="comment">// 0x000f0000 [19:16] NUMRSPAIR    (0x1) reads as `ImpDef</span></div>
<div class="line"><a id="l01276" name="l01276"></a><span class="lineno"> 1276</span>    <span class="comment">// 0x0000f000 [15:12] NUMPC        (0x4) reads as `ImpDef</span></div>
<div class="line"><a id="l01277" name="l01277"></a><span class="lineno"> 1277</span>    <span class="comment">// 0x00000100 [8]     SUPPDAC      (0) reads as `ImpDef</span></div>
<div class="line"><a id="l01278" name="l01278"></a><span class="lineno"> 1278</span>    <span class="comment">// 0x000000f0 [7:4]   NUMDVC       (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01279" name="l01279"></a><span class="lineno"> 1279</span>    <span class="comment">// 0x0000000f [3:0]   NUMACPAIRS   (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01280" name="l01280"></a><span class="lineno"> 1280</span>    io_ro_32 trcidr4;</div>
<div class="line"><a id="l01281" name="l01281"></a><span class="lineno"> 1281</span> </div>
<div class="line"><a id="l01282" name="l01282"></a><span class="lineno"> 1282</span>    _REG_(M33_TRCIDR5_OFFSET) <span class="comment">// M33_TRCIDR5</span></div>
<div class="line"><a id="l01283" name="l01283"></a><span class="lineno"> 1283</span>    <span class="comment">// TRCIDR5</span></div>
<div class="line"><a id="l01284" name="l01284"></a><span class="lineno"> 1284</span>    <span class="comment">// 0x80000000 [31]    REDFUNCNTR   (1) reads as `ImpDef</span></div>
<div class="line"><a id="l01285" name="l01285"></a><span class="lineno"> 1285</span>    <span class="comment">// 0x70000000 [30:28] NUMCNTR      (0x1) reads as `ImpDef</span></div>
<div class="line"><a id="l01286" name="l01286"></a><span class="lineno"> 1286</span>    <span class="comment">// 0x0e000000 [27:25] NUMSEQSTATE  (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01287" name="l01287"></a><span class="lineno"> 1287</span>    <span class="comment">// 0x00800000 [23]    LPOVERRIDE   (1) reads as `ImpDef</span></div>
<div class="line"><a id="l01288" name="l01288"></a><span class="lineno"> 1288</span>    <span class="comment">// 0x00400000 [22]    ATBTRIG      (1) reads as `ImpDef</span></div>
<div class="line"><a id="l01289" name="l01289"></a><span class="lineno"> 1289</span>    <span class="comment">// 0x003f0000 [21:16] TRACEIDSIZE  (0x07) reads as 0x07</span></div>
<div class="line"><a id="l01290" name="l01290"></a><span class="lineno"> 1290</span>    <span class="comment">// 0x00000e00 [11:9]  NUMEXTINSEL  (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01291" name="l01291"></a><span class="lineno"> 1291</span>    <span class="comment">// 0x000001ff [8:0]   NUMEXTIN     (0x004) reads as `ImpDef</span></div>
<div class="line"><a id="l01292" name="l01292"></a><span class="lineno"> 1292</span>    io_ro_32 trcidr5;</div>
<div class="line"><a id="l01293" name="l01293"></a><span class="lineno"> 1293</span> </div>
<div class="line"><a id="l01294" name="l01294"></a><span class="lineno"> 1294</span>    _REG_(M33_TRCIDR6_OFFSET) <span class="comment">// M33_TRCIDR6</span></div>
<div class="line"><a id="l01295" name="l01295"></a><span class="lineno"> 1295</span>    <span class="comment">// TRCIDR6</span></div>
<div class="line"><a id="l01296" name="l01296"></a><span class="lineno"> 1296</span>    <span class="comment">// 0x00000000 [31:0]  TRCIDR6      (0x00000000) </span></div>
<div class="line"><a id="l01297" name="l01297"></a><span class="lineno"> 1297</span>    io_rw_32 trcidr6;</div>
<div class="line"><a id="l01298" name="l01298"></a><span class="lineno"> 1298</span> </div>
<div class="line"><a id="l01299" name="l01299"></a><span class="lineno"> 1299</span>    _REG_(M33_TRCIDR7_OFFSET) <span class="comment">// M33_TRCIDR7</span></div>
<div class="line"><a id="l01300" name="l01300"></a><span class="lineno"> 1300</span>    <span class="comment">// TRCIDR7</span></div>
<div class="line"><a id="l01301" name="l01301"></a><span class="lineno"> 1301</span>    <span class="comment">// 0x00000000 [31:0]  TRCIDR7      (0x00000000) </span></div>
<div class="line"><a id="l01302" name="l01302"></a><span class="lineno"> 1302</span>    io_rw_32 trcidr7;</div>
<div class="line"><a id="l01303" name="l01303"></a><span class="lineno"> 1303</span> </div>
<div class="line"><a id="l01304" name="l01304"></a><span class="lineno"> 1304</span>    uint32_t _pad52[2];</div>
<div class="line"><a id="l01305" name="l01305"></a><span class="lineno"> 1305</span> </div>
<div class="line"><a id="l01306" name="l01306"></a><span class="lineno"> 1306</span>    <span class="comment">// (Description copied from array index 0 register M33_TRCRSCTLR2 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l01307" name="l01307"></a><span class="lineno"> 1307</span>    _REG_(M33_TRCRSCTLR2_OFFSET) <span class="comment">// M33_TRCRSCTLR2</span></div>
<div class="line"><a id="l01308" name="l01308"></a><span class="lineno"> 1308</span>    <span class="comment">// The TRCRSCTLR controls the trace resources</span></div>
<div class="line"><a id="l01309" name="l01309"></a><span class="lineno"> 1309</span>    <span class="comment">// 0x00200000 [21]    PAIRINV      (0) Inverts the result of a combined pair of resources</span></div>
<div class="line"><a id="l01310" name="l01310"></a><span class="lineno"> 1310</span>    <span class="comment">// 0x00100000 [20]    INV          (0) Inverts the selected resources</span></div>
<div class="line"><a id="l01311" name="l01311"></a><span class="lineno"> 1311</span>    <span class="comment">// 0x00070000 [18:16] GROUP        (0x0) Selects a group of resource</span></div>
<div class="line"><a id="l01312" name="l01312"></a><span class="lineno"> 1312</span>    <span class="comment">// 0x000000ff [7:0]   SELECT       (0x00) Selects one or more resources from the wanted group</span></div>
<div class="line"><a id="l01313" name="l01313"></a><span class="lineno"> 1313</span>    io_rw_32 trcrsctlr[2];</div>
<div class="line"><a id="l01314" name="l01314"></a><span class="lineno"> 1314</span> </div>
<div class="line"><a id="l01315" name="l01315"></a><span class="lineno"> 1315</span>    uint32_t _pad53[36];</div>
<div class="line"><a id="l01316" name="l01316"></a><span class="lineno"> 1316</span> </div>
<div class="line"><a id="l01317" name="l01317"></a><span class="lineno"> 1317</span>    _REG_(M33_TRCSSCSR_OFFSET) <span class="comment">// M33_TRCSSCSR</span></div>
<div class="line"><a id="l01318" name="l01318"></a><span class="lineno"> 1318</span>    <span class="comment">// Controls the corresponding single-shot comparator resource</span></div>
<div class="line"><a id="l01319" name="l01319"></a><span class="lineno"> 1319</span>    <span class="comment">// 0x80000000 [31]    STATUS       (0) Single-shot status bit</span></div>
<div class="line"><a id="l01320" name="l01320"></a><span class="lineno"> 1320</span>    <span class="comment">// 0x00000008 [3]     PC           (0) Reserved, RES1</span></div>
<div class="line"><a id="l01321" name="l01321"></a><span class="lineno"> 1321</span>    <span class="comment">// 0x00000004 [2]     DV           (0) Reserved, RES0</span></div>
<div class="line"><a id="l01322" name="l01322"></a><span class="lineno"> 1322</span>    <span class="comment">// 0x00000002 [1]     DA           (0) Reserved, RES0</span></div>
<div class="line"><a id="l01323" name="l01323"></a><span class="lineno"> 1323</span>    <span class="comment">// 0x00000001 [0]     INST         (0) Reserved, RES0</span></div>
<div class="line"><a id="l01324" name="l01324"></a><span class="lineno"> 1324</span>    io_rw_32 trcsscsr;</div>
<div class="line"><a id="l01325" name="l01325"></a><span class="lineno"> 1325</span> </div>
<div class="line"><a id="l01326" name="l01326"></a><span class="lineno"> 1326</span>    uint32_t _pad54[7];</div>
<div class="line"><a id="l01327" name="l01327"></a><span class="lineno"> 1327</span> </div>
<div class="line"><a id="l01328" name="l01328"></a><span class="lineno"> 1328</span>    _REG_(M33_TRCSSPCICR_OFFSET) <span class="comment">// M33_TRCSSPCICR</span></div>
<div class="line"><a id="l01329" name="l01329"></a><span class="lineno"> 1329</span>    <span class="comment">// Selects the PE comparator inputs for Single-shot control</span></div>
<div class="line"><a id="l01330" name="l01330"></a><span class="lineno"> 1330</span>    <span class="comment">// 0x0000000f [3:0]   PC           (0x0) Selects one or more PE comparator inputs for Single-shot control</span></div>
<div class="line"><a id="l01331" name="l01331"></a><span class="lineno"> 1331</span>    io_rw_32 trcsspcicr;</div>
<div class="line"><a id="l01332" name="l01332"></a><span class="lineno"> 1332</span> </div>
<div class="line"><a id="l01333" name="l01333"></a><span class="lineno"> 1333</span>    uint32_t _pad55[19];</div>
<div class="line"><a id="l01334" name="l01334"></a><span class="lineno"> 1334</span> </div>
<div class="line"><a id="l01335" name="l01335"></a><span class="lineno"> 1335</span>    _REG_(M33_TRCPDCR_OFFSET) <span class="comment">// M33_TRCPDCR</span></div>
<div class="line"><a id="l01336" name="l01336"></a><span class="lineno"> 1336</span>    <span class="comment">// Requests the system to provide power to the trace unit</span></div>
<div class="line"><a id="l01337" name="l01337"></a><span class="lineno"> 1337</span>    <span class="comment">// 0x00000008 [3]     PU           (0) Powerup request bit:</span></div>
<div class="line"><a id="l01338" name="l01338"></a><span class="lineno"> 1338</span>    io_rw_32 trcpdcr;</div>
<div class="line"><a id="l01339" name="l01339"></a><span class="lineno"> 1339</span> </div>
<div class="line"><a id="l01340" name="l01340"></a><span class="lineno"> 1340</span>    _REG_(M33_TRCPDSR_OFFSET) <span class="comment">// M33_TRCPDSR</span></div>
<div class="line"><a id="l01341" name="l01341"></a><span class="lineno"> 1341</span>    <span class="comment">// Returns the following information about the trace unit: - OS Lock status</span></div>
<div class="line"><a id="l01342" name="l01342"></a><span class="lineno"> 1342</span>    <span class="comment">// 0x00000020 [5]     OSLK         (0) OS Lock status bit:</span></div>
<div class="line"><a id="l01343" name="l01343"></a><span class="lineno"> 1343</span>    <span class="comment">// 0x00000002 [1]     STICKYPD     (1) Sticky powerdown status bit</span></div>
<div class="line"><a id="l01344" name="l01344"></a><span class="lineno"> 1344</span>    <span class="comment">// 0x00000001 [0]     POWER        (1) Power status bit:</span></div>
<div class="line"><a id="l01345" name="l01345"></a><span class="lineno"> 1345</span>    io_ro_32 trcpdsr;</div>
<div class="line"><a id="l01346" name="l01346"></a><span class="lineno"> 1346</span> </div>
<div class="line"><a id="l01347" name="l01347"></a><span class="lineno"> 1347</span>    uint32_t _pad56[755];</div>
<div class="line"><a id="l01348" name="l01348"></a><span class="lineno"> 1348</span> </div>
<div class="line"><a id="l01349" name="l01349"></a><span class="lineno"> 1349</span>    _REG_(M33_TRCITATBIDR_OFFSET) <span class="comment">// M33_TRCITATBIDR</span></div>
<div class="line"><a id="l01350" name="l01350"></a><span class="lineno"> 1350</span>    <span class="comment">// Trace Integration ATB Identification Register</span></div>
<div class="line"><a id="l01351" name="l01351"></a><span class="lineno"> 1351</span>    <span class="comment">// 0x0000007f [6:0]   ID           (0x00) Trace ID</span></div>
<div class="line"><a id="l01352" name="l01352"></a><span class="lineno"> 1352</span>    io_rw_32 trcitatbidr;</div>
<div class="line"><a id="l01353" name="l01353"></a><span class="lineno"> 1353</span> </div>
<div class="line"><a id="l01354" name="l01354"></a><span class="lineno"> 1354</span>    uint32_t _pad57[3];</div>
<div class="line"><a id="l01355" name="l01355"></a><span class="lineno"> 1355</span> </div>
<div class="line"><a id="l01356" name="l01356"></a><span class="lineno"> 1356</span>    _REG_(M33_TRCITIATBINR_OFFSET) <span class="comment">// M33_TRCITIATBINR</span></div>
<div class="line"><a id="l01357" name="l01357"></a><span class="lineno"> 1357</span>    <span class="comment">// Trace Integration Instruction ATB In Register</span></div>
<div class="line"><a id="l01358" name="l01358"></a><span class="lineno"> 1358</span>    <span class="comment">// 0x00000002 [1]     AFVALIDM     (0) Integration Mode instruction AFVALIDM in</span></div>
<div class="line"><a id="l01359" name="l01359"></a><span class="lineno"> 1359</span>    <span class="comment">// 0x00000001 [0]     ATREADYM     (0) Integration Mode instruction ATREADYM in</span></div>
<div class="line"><a id="l01360" name="l01360"></a><span class="lineno"> 1360</span>    io_rw_32 trcitiatbinr;</div>
<div class="line"><a id="l01361" name="l01361"></a><span class="lineno"> 1361</span> </div>
<div class="line"><a id="l01362" name="l01362"></a><span class="lineno"> 1362</span>    uint32_t _pad58;</div>
<div class="line"><a id="l01363" name="l01363"></a><span class="lineno"> 1363</span> </div>
<div class="line"><a id="l01364" name="l01364"></a><span class="lineno"> 1364</span>    _REG_(M33_TRCITIATBOUTR_OFFSET) <span class="comment">// M33_TRCITIATBOUTR</span></div>
<div class="line"><a id="l01365" name="l01365"></a><span class="lineno"> 1365</span>    <span class="comment">// Trace Integration Instruction ATB Out Register</span></div>
<div class="line"><a id="l01366" name="l01366"></a><span class="lineno"> 1366</span>    <span class="comment">// 0x00000002 [1]     AFREADY      (0) Integration Mode instruction AFREADY out</span></div>
<div class="line"><a id="l01367" name="l01367"></a><span class="lineno"> 1367</span>    <span class="comment">// 0x00000001 [0]     ATVALID      (0) Integration Mode instruction ATVALID out</span></div>
<div class="line"><a id="l01368" name="l01368"></a><span class="lineno"> 1368</span>    io_rw_32 trcitiatboutr;</div>
<div class="line"><a id="l01369" name="l01369"></a><span class="lineno"> 1369</span> </div>
<div class="line"><a id="l01370" name="l01370"></a><span class="lineno"> 1370</span>    uint32_t _pad59[40];</div>
<div class="line"><a id="l01371" name="l01371"></a><span class="lineno"> 1371</span> </div>
<div class="line"><a id="l01372" name="l01372"></a><span class="lineno"> 1372</span>    _REG_(M33_TRCCLAIMSET_OFFSET) <span class="comment">// M33_TRCCLAIMSET</span></div>
<div class="line"><a id="l01373" name="l01373"></a><span class="lineno"> 1373</span>    <span class="comment">// Claim Tag Set Register</span></div>
<div class="line"><a id="l01374" name="l01374"></a><span class="lineno"> 1374</span>    <span class="comment">// 0x00000008 [3]     SET3         (1) When a write to one of these bits occurs, with the value:</span></div>
<div class="line"><a id="l01375" name="l01375"></a><span class="lineno"> 1375</span>    <span class="comment">// 0x00000004 [2]     SET2         (1) When a write to one of these bits occurs, with the value:</span></div>
<div class="line"><a id="l01376" name="l01376"></a><span class="lineno"> 1376</span>    <span class="comment">// 0x00000002 [1]     SET1         (1) When a write to one of these bits occurs, with the value:</span></div>
<div class="line"><a id="l01377" name="l01377"></a><span class="lineno"> 1377</span>    <span class="comment">// 0x00000001 [0]     SET0         (1) When a write to one of these bits occurs, with the value:</span></div>
<div class="line"><a id="l01378" name="l01378"></a><span class="lineno"> 1378</span>    io_rw_32 trcclaimset;</div>
<div class="line"><a id="l01379" name="l01379"></a><span class="lineno"> 1379</span> </div>
<div class="line"><a id="l01380" name="l01380"></a><span class="lineno"> 1380</span>    _REG_(M33_TRCCLAIMCLR_OFFSET) <span class="comment">// M33_TRCCLAIMCLR</span></div>
<div class="line"><a id="l01381" name="l01381"></a><span class="lineno"> 1381</span>    <span class="comment">// Claim Tag Clear Register</span></div>
<div class="line"><a id="l01382" name="l01382"></a><span class="lineno"> 1382</span>    <span class="comment">// 0x00000008 [3]     CLR3         (0) When a write to one of these bits occurs, with the value:</span></div>
<div class="line"><a id="l01383" name="l01383"></a><span class="lineno"> 1383</span>    <span class="comment">// 0x00000004 [2]     CLR2         (0) When a write to one of these bits occurs, with the value:</span></div>
<div class="line"><a id="l01384" name="l01384"></a><span class="lineno"> 1384</span>    <span class="comment">// 0x00000002 [1]     CLR1         (0) When a write to one of these bits occurs, with the value:</span></div>
<div class="line"><a id="l01385" name="l01385"></a><span class="lineno"> 1385</span>    <span class="comment">// 0x00000001 [0]     CLR0         (0) When a write to one of these bits occurs, with the value:</span></div>
<div class="line"><a id="l01386" name="l01386"></a><span class="lineno"> 1386</span>    io_rw_32 trcclaimclr;</div>
<div class="line"><a id="l01387" name="l01387"></a><span class="lineno"> 1387</span> </div>
<div class="line"><a id="l01388" name="l01388"></a><span class="lineno"> 1388</span>    uint32_t _pad60[4];</div>
<div class="line"><a id="l01389" name="l01389"></a><span class="lineno"> 1389</span> </div>
<div class="line"><a id="l01390" name="l01390"></a><span class="lineno"> 1390</span>    _REG_(M33_TRCAUTHSTATUS_OFFSET) <span class="comment">// M33_TRCAUTHSTATUS</span></div>
<div class="line"><a id="l01391" name="l01391"></a><span class="lineno"> 1391</span>    <span class="comment">// Returns the level of tracing that the trace unit can support</span></div>
<div class="line"><a id="l01392" name="l01392"></a><span class="lineno"> 1392</span>    <span class="comment">// 0x000000c0 [7:6]   SNID         (0x0) Indicates whether the system enables the trace unit to...</span></div>
<div class="line"><a id="l01393" name="l01393"></a><span class="lineno"> 1393</span>    <span class="comment">// 0x00000030 [5:4]   SID          (0x0) Indicates whether the trace unit supports Secure invasive debug:</span></div>
<div class="line"><a id="l01394" name="l01394"></a><span class="lineno"> 1394</span>    <span class="comment">// 0x0000000c [3:2]   NSNID        (0x0) Indicates whether the system enables the trace unit to...</span></div>
<div class="line"><a id="l01395" name="l01395"></a><span class="lineno"> 1395</span>    <span class="comment">// 0x00000003 [1:0]   NSID         (0x0) Indicates whether the trace unit supports Non-secure...</span></div>
<div class="line"><a id="l01396" name="l01396"></a><span class="lineno"> 1396</span>    io_ro_32 trcauthstatus;</div>
<div class="line"><a id="l01397" name="l01397"></a><span class="lineno"> 1397</span> </div>
<div class="line"><a id="l01398" name="l01398"></a><span class="lineno"> 1398</span>    _REG_(M33_TRCDEVARCH_OFFSET) <span class="comment">// M33_TRCDEVARCH</span></div>
<div class="line"><a id="l01399" name="l01399"></a><span class="lineno"> 1399</span>    <span class="comment">// TRCDEVARCH</span></div>
<div class="line"><a id="l01400" name="l01400"></a><span class="lineno"> 1400</span>    <span class="comment">// 0xffe00000 [31:21] ARCHITECT    (0x23b) reads as 0b01000111011</span></div>
<div class="line"><a id="l01401" name="l01401"></a><span class="lineno"> 1401</span>    <span class="comment">// 0x00100000 [20]    PRESENT      (1) reads as 0b1</span></div>
<div class="line"><a id="l01402" name="l01402"></a><span class="lineno"> 1402</span>    <span class="comment">// 0x000f0000 [19:16] REVISION     (0x2) reads as 0b0000</span></div>
<div class="line"><a id="l01403" name="l01403"></a><span class="lineno"> 1403</span>    <span class="comment">// 0x0000ffff [15:0]  ARCHID       (0x4a13) reads as 0b0100101000010011</span></div>
<div class="line"><a id="l01404" name="l01404"></a><span class="lineno"> 1404</span>    io_ro_32 trcdevarch;</div>
<div class="line"><a id="l01405" name="l01405"></a><span class="lineno"> 1405</span> </div>
<div class="line"><a id="l01406" name="l01406"></a><span class="lineno"> 1406</span>    uint32_t _pad61[2];</div>
<div class="line"><a id="l01407" name="l01407"></a><span class="lineno"> 1407</span> </div>
<div class="line"><a id="l01408" name="l01408"></a><span class="lineno"> 1408</span>    _REG_(M33_TRCDEVID_OFFSET) <span class="comment">// M33_TRCDEVID</span></div>
<div class="line"><a id="l01409" name="l01409"></a><span class="lineno"> 1409</span>    <span class="comment">// TRCDEVID</span></div>
<div class="line"><a id="l01410" name="l01410"></a><span class="lineno"> 1410</span>    <span class="comment">// 0x00000000 [31:0]  TRCDEVID     (0x00000000) </span></div>
<div class="line"><a id="l01411" name="l01411"></a><span class="lineno"> 1411</span>    io_rw_32 trcdevid;</div>
<div class="line"><a id="l01412" name="l01412"></a><span class="lineno"> 1412</span> </div>
<div class="line"><a id="l01413" name="l01413"></a><span class="lineno"> 1413</span>    _REG_(M33_TRCDEVTYPE_OFFSET) <span class="comment">// M33_TRCDEVTYPE</span></div>
<div class="line"><a id="l01414" name="l01414"></a><span class="lineno"> 1414</span>    <span class="comment">// TRCDEVTYPE</span></div>
<div class="line"><a id="l01415" name="l01415"></a><span class="lineno"> 1415</span>    <span class="comment">// 0x000000f0 [7:4]   SUB          (0x1) reads as 0b0001</span></div>
<div class="line"><a id="l01416" name="l01416"></a><span class="lineno"> 1416</span>    <span class="comment">// 0x0000000f [3:0]   MAJOR        (0x3) reads as 0b0011</span></div>
<div class="line"><a id="l01417" name="l01417"></a><span class="lineno"> 1417</span>    io_ro_32 trcdevtype;</div>
<div class="line"><a id="l01418" name="l01418"></a><span class="lineno"> 1418</span> </div>
<div class="line"><a id="l01419" name="l01419"></a><span class="lineno"> 1419</span>    _REG_(M33_TRCPIDR4_OFFSET) <span class="comment">// M33_TRCPIDR4</span></div>
<div class="line"><a id="l01420" name="l01420"></a><span class="lineno"> 1420</span>    <span class="comment">// TRCPIDR4</span></div>
<div class="line"><a id="l01421" name="l01421"></a><span class="lineno"> 1421</span>    <span class="comment">// 0x000000f0 [7:4]   SIZE         (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01422" name="l01422"></a><span class="lineno"> 1422</span>    <span class="comment">// 0x0000000f [3:0]   DES_2        (0x4) reads as `ImpDef</span></div>
<div class="line"><a id="l01423" name="l01423"></a><span class="lineno"> 1423</span>    io_ro_32 trcpidr4;</div>
<div class="line"><a id="l01424" name="l01424"></a><span class="lineno"> 1424</span> </div>
<div class="line"><a id="l01425" name="l01425"></a><span class="lineno"> 1425</span>    _REG_(M33_TRCPIDR5_OFFSET) <span class="comment">// M33_TRCPIDR5</span></div>
<div class="line"><a id="l01426" name="l01426"></a><span class="lineno"> 1426</span>    <span class="comment">// TRCPIDR5</span></div>
<div class="line"><a id="l01427" name="l01427"></a><span class="lineno"> 1427</span>    <span class="comment">// 0x00000000 [31:0]  TRCPIDR5     (0x00000000) </span></div>
<div class="line"><a id="l01428" name="l01428"></a><span class="lineno"> 1428</span>    io_rw_32 trcpidr5;</div>
<div class="line"><a id="l01429" name="l01429"></a><span class="lineno"> 1429</span> </div>
<div class="line"><a id="l01430" name="l01430"></a><span class="lineno"> 1430</span>    _REG_(M33_TRCPIDR6_OFFSET) <span class="comment">// M33_TRCPIDR6</span></div>
<div class="line"><a id="l01431" name="l01431"></a><span class="lineno"> 1431</span>    <span class="comment">// TRCPIDR6</span></div>
<div class="line"><a id="l01432" name="l01432"></a><span class="lineno"> 1432</span>    <span class="comment">// 0x00000000 [31:0]  TRCPIDR6     (0x00000000) </span></div>
<div class="line"><a id="l01433" name="l01433"></a><span class="lineno"> 1433</span>    io_rw_32 trcpidr6;</div>
<div class="line"><a id="l01434" name="l01434"></a><span class="lineno"> 1434</span> </div>
<div class="line"><a id="l01435" name="l01435"></a><span class="lineno"> 1435</span>    _REG_(M33_TRCPIDR7_OFFSET) <span class="comment">// M33_TRCPIDR7</span></div>
<div class="line"><a id="l01436" name="l01436"></a><span class="lineno"> 1436</span>    <span class="comment">// TRCPIDR7</span></div>
<div class="line"><a id="l01437" name="l01437"></a><span class="lineno"> 1437</span>    <span class="comment">// 0x00000000 [31:0]  TRCPIDR7     (0x00000000) </span></div>
<div class="line"><a id="l01438" name="l01438"></a><span class="lineno"> 1438</span>    io_rw_32 trcpidr7;</div>
<div class="line"><a id="l01439" name="l01439"></a><span class="lineno"> 1439</span> </div>
<div class="line"><a id="l01440" name="l01440"></a><span class="lineno"> 1440</span>    _REG_(M33_TRCPIDR0_OFFSET) <span class="comment">// M33_TRCPIDR0</span></div>
<div class="line"><a id="l01441" name="l01441"></a><span class="lineno"> 1441</span>    <span class="comment">// TRCPIDR0</span></div>
<div class="line"><a id="l01442" name="l01442"></a><span class="lineno"> 1442</span>    <span class="comment">// 0x000000ff [7:0]   PART_0       (0x21) reads as `ImpDef</span></div>
<div class="line"><a id="l01443" name="l01443"></a><span class="lineno"> 1443</span>    io_ro_32 trcpidr0;</div>
<div class="line"><a id="l01444" name="l01444"></a><span class="lineno"> 1444</span> </div>
<div class="line"><a id="l01445" name="l01445"></a><span class="lineno"> 1445</span>    _REG_(M33_TRCPIDR1_OFFSET) <span class="comment">// M33_TRCPIDR1</span></div>
<div class="line"><a id="l01446" name="l01446"></a><span class="lineno"> 1446</span>    <span class="comment">// TRCPIDR1</span></div>
<div class="line"><a id="l01447" name="l01447"></a><span class="lineno"> 1447</span>    <span class="comment">// 0x000000f0 [7:4]   DES_0        (0xb) reads as `ImpDef</span></div>
<div class="line"><a id="l01448" name="l01448"></a><span class="lineno"> 1448</span>    <span class="comment">// 0x0000000f [3:0]   PART_0       (0xd) reads as `ImpDef</span></div>
<div class="line"><a id="l01449" name="l01449"></a><span class="lineno"> 1449</span>    io_ro_32 trcpidr1;</div>
<div class="line"><a id="l01450" name="l01450"></a><span class="lineno"> 1450</span> </div>
<div class="line"><a id="l01451" name="l01451"></a><span class="lineno"> 1451</span>    _REG_(M33_TRCPIDR2_OFFSET) <span class="comment">// M33_TRCPIDR2</span></div>
<div class="line"><a id="l01452" name="l01452"></a><span class="lineno"> 1452</span>    <span class="comment">// TRCPIDR2</span></div>
<div class="line"><a id="l01453" name="l01453"></a><span class="lineno"> 1453</span>    <span class="comment">// 0x000000f0 [7:4]   REVISION     (0x2) reads as `ImpDef</span></div>
<div class="line"><a id="l01454" name="l01454"></a><span class="lineno"> 1454</span>    <span class="comment">// 0x00000008 [3]     JEDEC        (1) reads as 0b1</span></div>
<div class="line"><a id="l01455" name="l01455"></a><span class="lineno"> 1455</span>    <span class="comment">// 0x00000007 [2:0]   DES_0        (0x3) reads as `ImpDef</span></div>
<div class="line"><a id="l01456" name="l01456"></a><span class="lineno"> 1456</span>    io_ro_32 trcpidr2;</div>
<div class="line"><a id="l01457" name="l01457"></a><span class="lineno"> 1457</span> </div>
<div class="line"><a id="l01458" name="l01458"></a><span class="lineno"> 1458</span>    _REG_(M33_TRCPIDR3_OFFSET) <span class="comment">// M33_TRCPIDR3</span></div>
<div class="line"><a id="l01459" name="l01459"></a><span class="lineno"> 1459</span>    <span class="comment">// TRCPIDR3</span></div>
<div class="line"><a id="l01460" name="l01460"></a><span class="lineno"> 1460</span>    <span class="comment">// 0x000000f0 [7:4]   REVAND       (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01461" name="l01461"></a><span class="lineno"> 1461</span>    <span class="comment">// 0x0000000f [3:0]   CMOD         (0x0) reads as `ImpDef</span></div>
<div class="line"><a id="l01462" name="l01462"></a><span class="lineno"> 1462</span>    io_ro_32 trcpidr3;</div>
<div class="line"><a id="l01463" name="l01463"></a><span class="lineno"> 1463</span> </div>
<div class="line"><a id="l01464" name="l01464"></a><span class="lineno"> 1464</span>    <span class="comment">// (Description copied from array index 0 register M33_TRCCIDR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l01465" name="l01465"></a><span class="lineno"> 1465</span>    _REG_(M33_TRCCIDR0_OFFSET) <span class="comment">// M33_TRCCIDR0</span></div>
<div class="line"><a id="l01466" name="l01466"></a><span class="lineno"> 1466</span>    <span class="comment">// TRCCIDR0</span></div>
<div class="line"><a id="l01467" name="l01467"></a><span class="lineno"> 1467</span>    <span class="comment">// 0x000000ff [7:0]   PRMBL_0      (0x0d) reads as 0b00001101</span></div>
<div class="line"><a id="l01468" name="l01468"></a><span class="lineno"> 1468</span>    io_ro_32 trccidr[4];</div>
<div class="line"><a id="l01469" name="l01469"></a><span class="lineno"> 1469</span> </div>
<div class="line"><a id="l01470" name="l01470"></a><span class="lineno"> 1470</span>    _REG_(M33_CTICONTROL_OFFSET) <span class="comment">// M33_CTICONTROL</span></div>
<div class="line"><a id="l01471" name="l01471"></a><span class="lineno"> 1471</span>    <span class="comment">// CTI Control Register</span></div>
<div class="line"><a id="l01472" name="l01472"></a><span class="lineno"> 1472</span>    <span class="comment">// 0x00000001 [0]     GLBEN        (0) Enables or disables the CTI</span></div>
<div class="line"><a id="l01473" name="l01473"></a><span class="lineno"> 1473</span>    io_rw_32 cticontrol;</div>
<div class="line"><a id="l01474" name="l01474"></a><span class="lineno"> 1474</span> </div>
<div class="line"><a id="l01475" name="l01475"></a><span class="lineno"> 1475</span>    uint32_t _pad62[3];</div>
<div class="line"><a id="l01476" name="l01476"></a><span class="lineno"> 1476</span> </div>
<div class="line"><a id="l01477" name="l01477"></a><span class="lineno"> 1477</span>    _REG_(M33_CTIINTACK_OFFSET) <span class="comment">// M33_CTIINTACK</span></div>
<div class="line"><a id="l01478" name="l01478"></a><span class="lineno"> 1478</span>    <span class="comment">// CTI Interrupt Acknowledge Register</span></div>
<div class="line"><a id="l01479" name="l01479"></a><span class="lineno"> 1479</span>    <span class="comment">// 0x000000ff [7:0]   INTACK       (0x00) Acknowledges the corresponding ctitrigout output</span></div>
<div class="line"><a id="l01480" name="l01480"></a><span class="lineno"> 1480</span>    io_rw_32 ctiintack;</div>
<div class="line"><a id="l01481" name="l01481"></a><span class="lineno"> 1481</span> </div>
<div class="line"><a id="l01482" name="l01482"></a><span class="lineno"> 1482</span>    _REG_(M33_CTIAPPSET_OFFSET) <span class="comment">// M33_CTIAPPSET</span></div>
<div class="line"><a id="l01483" name="l01483"></a><span class="lineno"> 1483</span>    <span class="comment">// CTI Application Trigger Set Register</span></div>
<div class="line"><a id="l01484" name="l01484"></a><span class="lineno"> 1484</span>    <span class="comment">// 0x0000000f [3:0]   APPSET       (0x0) Setting a bit HIGH generates a channel event for the...</span></div>
<div class="line"><a id="l01485" name="l01485"></a><span class="lineno"> 1485</span>    io_rw_32 ctiappset;</div>
<div class="line"><a id="l01486" name="l01486"></a><span class="lineno"> 1486</span> </div>
<div class="line"><a id="l01487" name="l01487"></a><span class="lineno"> 1487</span>    _REG_(M33_CTIAPPCLEAR_OFFSET) <span class="comment">// M33_CTIAPPCLEAR</span></div>
<div class="line"><a id="l01488" name="l01488"></a><span class="lineno"> 1488</span>    <span class="comment">// CTI Application Trigger Clear Register</span></div>
<div class="line"><a id="l01489" name="l01489"></a><span class="lineno"> 1489</span>    <span class="comment">// 0x0000000f [3:0]   APPCLEAR     (0x0) Sets the corresponding bits in the CTIAPPSET to 0</span></div>
<div class="line"><a id="l01490" name="l01490"></a><span class="lineno"> 1490</span>    io_rw_32 ctiappclear;</div>
<div class="line"><a id="l01491" name="l01491"></a><span class="lineno"> 1491</span> </div>
<div class="line"><a id="l01492" name="l01492"></a><span class="lineno"> 1492</span>    _REG_(M33_CTIAPPPULSE_OFFSET) <span class="comment">// M33_CTIAPPPULSE</span></div>
<div class="line"><a id="l01493" name="l01493"></a><span class="lineno"> 1493</span>    <span class="comment">// CTI Application Pulse Register</span></div>
<div class="line"><a id="l01494" name="l01494"></a><span class="lineno"> 1494</span>    <span class="comment">// 0x0000000f [3:0]   APPULSE      (0x0) Setting a bit HIGH generates a channel event pulse for...</span></div>
<div class="line"><a id="l01495" name="l01495"></a><span class="lineno"> 1495</span>    io_rw_32 ctiapppulse;</div>
<div class="line"><a id="l01496" name="l01496"></a><span class="lineno"> 1496</span> </div>
<div class="line"><a id="l01497" name="l01497"></a><span class="lineno"> 1497</span>    <span class="comment">// (Description copied from array index 0 register M33_CTIINEN0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l01498" name="l01498"></a><span class="lineno"> 1498</span>    _REG_(M33_CTIINEN0_OFFSET) <span class="comment">// M33_CTIINEN0</span></div>
<div class="line"><a id="l01499" name="l01499"></a><span class="lineno"> 1499</span>    <span class="comment">// CTI Trigger to Channel Enable Registers</span></div>
<div class="line"><a id="l01500" name="l01500"></a><span class="lineno"> 1500</span>    <span class="comment">// 0x0000000f [3:0]   TRIGINEN     (0x0) Enables a cross trigger event to the corresponding...</span></div>
<div class="line"><a id="l01501" name="l01501"></a><span class="lineno"> 1501</span>    io_rw_32 ctiinen[8];</div>
<div class="line"><a id="l01502" name="l01502"></a><span class="lineno"> 1502</span> </div>
<div class="line"><a id="l01503" name="l01503"></a><span class="lineno"> 1503</span>    uint32_t _pad63[24];</div>
<div class="line"><a id="l01504" name="l01504"></a><span class="lineno"> 1504</span> </div>
<div class="line"><a id="l01505" name="l01505"></a><span class="lineno"> 1505</span>    <span class="comment">// (Description copied from array index 0 register M33_CTIOUTEN0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l01506" name="l01506"></a><span class="lineno"> 1506</span>    _REG_(M33_CTIOUTEN0_OFFSET) <span class="comment">// M33_CTIOUTEN0</span></div>
<div class="line"><a id="l01507" name="l01507"></a><span class="lineno"> 1507</span>    <span class="comment">// CTI Trigger to Channel Enable Registers</span></div>
<div class="line"><a id="l01508" name="l01508"></a><span class="lineno"> 1508</span>    <span class="comment">// 0x0000000f [3:0]   TRIGOUTEN    (0x0) Enables a cross trigger event to ctitrigout when the...</span></div>
<div class="line"><a id="l01509" name="l01509"></a><span class="lineno"> 1509</span>    io_rw_32 ctiouten[8];</div>
<div class="line"><a id="l01510" name="l01510"></a><span class="lineno"> 1510</span> </div>
<div class="line"><a id="l01511" name="l01511"></a><span class="lineno"> 1511</span>    uint32_t _pad64[28];</div>
<div class="line"><a id="l01512" name="l01512"></a><span class="lineno"> 1512</span> </div>
<div class="line"><a id="l01513" name="l01513"></a><span class="lineno"> 1513</span>    _REG_(M33_CTITRIGINSTATUS_OFFSET) <span class="comment">// M33_CTITRIGINSTATUS</span></div>
<div class="line"><a id="l01514" name="l01514"></a><span class="lineno"> 1514</span>    <span class="comment">// CTI Trigger to Channel Enable Registers</span></div>
<div class="line"><a id="l01515" name="l01515"></a><span class="lineno"> 1515</span>    <span class="comment">// 0x000000ff [7:0]   TRIGINSTATUS (0x00) Shows the status of the ctitrigin inputs</span></div>
<div class="line"><a id="l01516" name="l01516"></a><span class="lineno"> 1516</span>    io_ro_32 ctitriginstatus;</div>
<div class="line"><a id="l01517" name="l01517"></a><span class="lineno"> 1517</span> </div>
<div class="line"><a id="l01518" name="l01518"></a><span class="lineno"> 1518</span>    _REG_(M33_CTITRIGOUTSTATUS_OFFSET) <span class="comment">// M33_CTITRIGOUTSTATUS</span></div>
<div class="line"><a id="l01519" name="l01519"></a><span class="lineno"> 1519</span>    <span class="comment">// CTI Trigger In Status Register</span></div>
<div class="line"><a id="l01520" name="l01520"></a><span class="lineno"> 1520</span>    <span class="comment">// 0x000000ff [7:0]   TRIGOUTSTATUS (0x00) Shows the status of the ctitrigout outputs</span></div>
<div class="line"><a id="l01521" name="l01521"></a><span class="lineno"> 1521</span>    io_ro_32 ctitrigoutstatus;</div>
<div class="line"><a id="l01522" name="l01522"></a><span class="lineno"> 1522</span> </div>
<div class="line"><a id="l01523" name="l01523"></a><span class="lineno"> 1523</span>    _REG_(M33_CTICHINSTATUS_OFFSET) <span class="comment">// M33_CTICHINSTATUS</span></div>
<div class="line"><a id="l01524" name="l01524"></a><span class="lineno"> 1524</span>    <span class="comment">// CTI Channel In Status Register</span></div>
<div class="line"><a id="l01525" name="l01525"></a><span class="lineno"> 1525</span>    <span class="comment">// 0x0000000f [3:0]   CTICHOUTSTATUS (0x0) Shows the status of the ctichout outputs</span></div>
<div class="line"><a id="l01526" name="l01526"></a><span class="lineno"> 1526</span>    io_ro_32 ctichinstatus;</div>
<div class="line"><a id="l01527" name="l01527"></a><span class="lineno"> 1527</span> </div>
<div class="line"><a id="l01528" name="l01528"></a><span class="lineno"> 1528</span>    uint32_t _pad65;</div>
<div class="line"><a id="l01529" name="l01529"></a><span class="lineno"> 1529</span> </div>
<div class="line"><a id="l01530" name="l01530"></a><span class="lineno"> 1530</span>    _REG_(M33_CTIGATE_OFFSET) <span class="comment">// M33_CTIGATE</span></div>
<div class="line"><a id="l01531" name="l01531"></a><span class="lineno"> 1531</span>    <span class="comment">// Enable CTI Channel Gate register</span></div>
<div class="line"><a id="l01532" name="l01532"></a><span class="lineno"> 1532</span>    <span class="comment">// 0x00000008 [3]     CTIGATEEN3   (1) Enable ctichout3</span></div>
<div class="line"><a id="l01533" name="l01533"></a><span class="lineno"> 1533</span>    <span class="comment">// 0x00000004 [2]     CTIGATEEN2   (1) Enable ctichout2</span></div>
<div class="line"><a id="l01534" name="l01534"></a><span class="lineno"> 1534</span>    <span class="comment">// 0x00000002 [1]     CTIGATEEN1   (1) Enable ctichout1</span></div>
<div class="line"><a id="l01535" name="l01535"></a><span class="lineno"> 1535</span>    <span class="comment">// 0x00000001 [0]     CTIGATEEN0   (1) Enable ctichout0</span></div>
<div class="line"><a id="l01536" name="l01536"></a><span class="lineno"> 1536</span>    io_rw_32 ctigate;</div>
<div class="line"><a id="l01537" name="l01537"></a><span class="lineno"> 1537</span> </div>
<div class="line"><a id="l01538" name="l01538"></a><span class="lineno"> 1538</span>    _REG_(M33_ASICCTL_OFFSET) <span class="comment">// M33_ASICCTL</span></div>
<div class="line"><a id="l01539" name="l01539"></a><span class="lineno"> 1539</span>    <span class="comment">// External Multiplexer Control register</span></div>
<div class="line"><a id="l01540" name="l01540"></a><span class="lineno"> 1540</span>    <span class="comment">// 0x00000000 [31:0]  ASICCTL      (0x00000000) </span></div>
<div class="line"><a id="l01541" name="l01541"></a><span class="lineno"> 1541</span>    io_rw_32 asicctl;</div>
<div class="line"><a id="l01542" name="l01542"></a><span class="lineno"> 1542</span> </div>
<div class="line"><a id="l01543" name="l01543"></a><span class="lineno"> 1543</span>    uint32_t _pad66[871];</div>
<div class="line"><a id="l01544" name="l01544"></a><span class="lineno"> 1544</span> </div>
<div class="line"><a id="l01545" name="l01545"></a><span class="lineno"> 1545</span>    _REG_(M33_ITCHOUT_OFFSET) <span class="comment">// M33_ITCHOUT</span></div>
<div class="line"><a id="l01546" name="l01546"></a><span class="lineno"> 1546</span>    <span class="comment">// Integration Test Channel Output register</span></div>
<div class="line"><a id="l01547" name="l01547"></a><span class="lineno"> 1547</span>    <span class="comment">// 0x0000000f [3:0]   CTCHOUT      (0x0) Sets the value of the ctichout outputs</span></div>
<div class="line"><a id="l01548" name="l01548"></a><span class="lineno"> 1548</span>    io_rw_32 itchout;</div>
<div class="line"><a id="l01549" name="l01549"></a><span class="lineno"> 1549</span> </div>
<div class="line"><a id="l01550" name="l01550"></a><span class="lineno"> 1550</span>    _REG_(M33_ITTRIGOUT_OFFSET) <span class="comment">// M33_ITTRIGOUT</span></div>
<div class="line"><a id="l01551" name="l01551"></a><span class="lineno"> 1551</span>    <span class="comment">// Integration Test Trigger Output register</span></div>
<div class="line"><a id="l01552" name="l01552"></a><span class="lineno"> 1552</span>    <span class="comment">// 0x000000ff [7:0]   CTTRIGOUT    (0x00) Sets the value of the ctitrigout outputs</span></div>
<div class="line"><a id="l01553" name="l01553"></a><span class="lineno"> 1553</span>    io_rw_32 ittrigout;</div>
<div class="line"><a id="l01554" name="l01554"></a><span class="lineno"> 1554</span> </div>
<div class="line"><a id="l01555" name="l01555"></a><span class="lineno"> 1555</span>    uint32_t _pad67[2];</div>
<div class="line"><a id="l01556" name="l01556"></a><span class="lineno"> 1556</span> </div>
<div class="line"><a id="l01557" name="l01557"></a><span class="lineno"> 1557</span>    _REG_(M33_ITCHIN_OFFSET) <span class="comment">// M33_ITCHIN</span></div>
<div class="line"><a id="l01558" name="l01558"></a><span class="lineno"> 1558</span>    <span class="comment">// Integration Test Channel Input register</span></div>
<div class="line"><a id="l01559" name="l01559"></a><span class="lineno"> 1559</span>    <span class="comment">// 0x0000000f [3:0]   CTCHIN       (0x0) Reads the value of the ctichin inputs</span></div>
<div class="line"><a id="l01560" name="l01560"></a><span class="lineno"> 1560</span>    io_ro_32 itchin;</div>
<div class="line"><a id="l01561" name="l01561"></a><span class="lineno"> 1561</span> </div>
<div class="line"><a id="l01562" name="l01562"></a><span class="lineno"> 1562</span>    uint32_t _pad68[2];</div>
<div class="line"><a id="l01563" name="l01563"></a><span class="lineno"> 1563</span> </div>
<div class="line"><a id="l01564" name="l01564"></a><span class="lineno"> 1564</span>    _REG_(M33_ITCTRL_OFFSET) <span class="comment">// M33_ITCTRL</span></div>
<div class="line"><a id="l01565" name="l01565"></a><span class="lineno"> 1565</span>    <span class="comment">// Integration Mode Control register</span></div>
<div class="line"><a id="l01566" name="l01566"></a><span class="lineno"> 1566</span>    <span class="comment">// 0x00000001 [0]     IME          (0) Integration Mode Enable</span></div>
<div class="line"><a id="l01567" name="l01567"></a><span class="lineno"> 1567</span>    io_rw_32 itctrl;</div>
<div class="line"><a id="l01568" name="l01568"></a><span class="lineno"> 1568</span> </div>
<div class="line"><a id="l01569" name="l01569"></a><span class="lineno"> 1569</span>    uint32_t _pad69[46];</div>
<div class="line"><a id="l01570" name="l01570"></a><span class="lineno"> 1570</span> </div>
<div class="line"><a id="l01571" name="l01571"></a><span class="lineno"> 1571</span>    _REG_(M33_DEVARCH_OFFSET) <span class="comment">// M33_DEVARCH</span></div>
<div class="line"><a id="l01572" name="l01572"></a><span class="lineno"> 1572</span>    <span class="comment">// Device Architecture register</span></div>
<div class="line"><a id="l01573" name="l01573"></a><span class="lineno"> 1573</span>    <span class="comment">// 0xffe00000 [31:21] ARCHITECT    (0x23b) Indicates the component architect</span></div>
<div class="line"><a id="l01574" name="l01574"></a><span class="lineno"> 1574</span>    <span class="comment">// 0x00100000 [20]    PRESENT      (1) Indicates whether the DEVARCH register is present</span></div>
<div class="line"><a id="l01575" name="l01575"></a><span class="lineno"> 1575</span>    <span class="comment">// 0x000f0000 [19:16] REVISION     (0x0) Indicates the architecture revision</span></div>
<div class="line"><a id="l01576" name="l01576"></a><span class="lineno"> 1576</span>    <span class="comment">// 0x0000ffff [15:0]  ARCHID       (0x1a14) Indicates the component</span></div>
<div class="line"><a id="l01577" name="l01577"></a><span class="lineno"> 1577</span>    io_ro_32 devarch;</div>
<div class="line"><a id="l01578" name="l01578"></a><span class="lineno"> 1578</span> </div>
<div class="line"><a id="l01579" name="l01579"></a><span class="lineno"> 1579</span>    uint32_t _pad70[2];</div>
<div class="line"><a id="l01580" name="l01580"></a><span class="lineno"> 1580</span> </div>
<div class="line"><a id="l01581" name="l01581"></a><span class="lineno"> 1581</span>    _REG_(M33_DEVID_OFFSET) <span class="comment">// M33_DEVID</span></div>
<div class="line"><a id="l01582" name="l01582"></a><span class="lineno"> 1582</span>    <span class="comment">// Device Configuration register</span></div>
<div class="line"><a id="l01583" name="l01583"></a><span class="lineno"> 1583</span>    <span class="comment">// 0x000f0000 [19:16] NUMCH        (0x4) Number of ECT channels available</span></div>
<div class="line"><a id="l01584" name="l01584"></a><span class="lineno"> 1584</span>    <span class="comment">// 0x0000ff00 [15:8]  NUMTRIG      (0x08) Number of ECT triggers available</span></div>
<div class="line"><a id="l01585" name="l01585"></a><span class="lineno"> 1585</span>    <span class="comment">// 0x0000001f [4:0]   EXTMUXNUM    (0x00) Indicates the number of multiplexers available on...</span></div>
<div class="line"><a id="l01586" name="l01586"></a><span class="lineno"> 1586</span>    io_ro_32 devid;</div>
<div class="line"><a id="l01587" name="l01587"></a><span class="lineno"> 1587</span> </div>
<div class="line"><a id="l01588" name="l01588"></a><span class="lineno"> 1588</span>    _REG_(M33_DEVTYPE_OFFSET) <span class="comment">// M33_DEVTYPE</span></div>
<div class="line"><a id="l01589" name="l01589"></a><span class="lineno"> 1589</span>    <span class="comment">// Device Type Identifier register</span></div>
<div class="line"><a id="l01590" name="l01590"></a><span class="lineno"> 1590</span>    <span class="comment">// 0x000000f0 [7:4]   SUB          (0x1) Sub-classification of the type of the debug component as...</span></div>
<div class="line"><a id="l01591" name="l01591"></a><span class="lineno"> 1591</span>    <span class="comment">// 0x0000000f [3:0]   MAJOR        (0x4) Major classification of the type of the debug component...</span></div>
<div class="line"><a id="l01592" name="l01592"></a><span class="lineno"> 1592</span>    io_ro_32 devtype;</div>
<div class="line"><a id="l01593" name="l01593"></a><span class="lineno"> 1593</span> </div>
<div class="line"><a id="l01594" name="l01594"></a><span class="lineno"> 1594</span>    _REG_(M33_PIDR4_OFFSET) <span class="comment">// M33_PIDR4</span></div>
<div class="line"><a id="l01595" name="l01595"></a><span class="lineno"> 1595</span>    <span class="comment">// CoreSight Peripheral ID4</span></div>
<div class="line"><a id="l01596" name="l01596"></a><span class="lineno"> 1596</span>    <span class="comment">// 0x000000f0 [7:4]   SIZE         (0x0) Always 0b0000</span></div>
<div class="line"><a id="l01597" name="l01597"></a><span class="lineno"> 1597</span>    <span class="comment">// 0x0000000f [3:0]   DES_2        (0x4) Together, PIDR1</span></div>
<div class="line"><a id="l01598" name="l01598"></a><span class="lineno"> 1598</span>    io_ro_32 pidr4;</div>
<div class="line"><a id="l01599" name="l01599"></a><span class="lineno"> 1599</span> </div>
<div class="line"><a id="l01600" name="l01600"></a><span class="lineno"> 1600</span>    _REG_(M33_PIDR5_OFFSET) <span class="comment">// M33_PIDR5</span></div>
<div class="line"><a id="l01601" name="l01601"></a><span class="lineno"> 1601</span>    <span class="comment">// CoreSight Peripheral ID5</span></div>
<div class="line"><a id="l01602" name="l01602"></a><span class="lineno"> 1602</span>    <span class="comment">// 0x00000000 [31:0]  PIDR5        (0x00000000) </span></div>
<div class="line"><a id="l01603" name="l01603"></a><span class="lineno"> 1603</span>    io_rw_32 pidr5;</div>
<div class="line"><a id="l01604" name="l01604"></a><span class="lineno"> 1604</span> </div>
<div class="line"><a id="l01605" name="l01605"></a><span class="lineno"> 1605</span>    _REG_(M33_PIDR6_OFFSET) <span class="comment">// M33_PIDR6</span></div>
<div class="line"><a id="l01606" name="l01606"></a><span class="lineno"> 1606</span>    <span class="comment">// CoreSight Peripheral ID6</span></div>
<div class="line"><a id="l01607" name="l01607"></a><span class="lineno"> 1607</span>    <span class="comment">// 0x00000000 [31:0]  PIDR6        (0x00000000) </span></div>
<div class="line"><a id="l01608" name="l01608"></a><span class="lineno"> 1608</span>    io_rw_32 pidr6;</div>
<div class="line"><a id="l01609" name="l01609"></a><span class="lineno"> 1609</span> </div>
<div class="line"><a id="l01610" name="l01610"></a><span class="lineno"> 1610</span>    _REG_(M33_PIDR7_OFFSET) <span class="comment">// M33_PIDR7</span></div>
<div class="line"><a id="l01611" name="l01611"></a><span class="lineno"> 1611</span>    <span class="comment">// CoreSight Peripheral ID7</span></div>
<div class="line"><a id="l01612" name="l01612"></a><span class="lineno"> 1612</span>    <span class="comment">// 0x00000000 [31:0]  PIDR7        (0x00000000) </span></div>
<div class="line"><a id="l01613" name="l01613"></a><span class="lineno"> 1613</span>    io_rw_32 pidr7;</div>
<div class="line"><a id="l01614" name="l01614"></a><span class="lineno"> 1614</span> </div>
<div class="line"><a id="l01615" name="l01615"></a><span class="lineno"> 1615</span>    _REG_(M33_PIDR0_OFFSET) <span class="comment">// M33_PIDR0</span></div>
<div class="line"><a id="l01616" name="l01616"></a><span class="lineno"> 1616</span>    <span class="comment">// CoreSight Peripheral ID0</span></div>
<div class="line"><a id="l01617" name="l01617"></a><span class="lineno"> 1617</span>    <span class="comment">// 0x000000ff [7:0]   PART_0       (0x21) Bits[7:0] of the 12-bit part number of the component</span></div>
<div class="line"><a id="l01618" name="l01618"></a><span class="lineno"> 1618</span>    io_ro_32 pidr0;</div>
<div class="line"><a id="l01619" name="l01619"></a><span class="lineno"> 1619</span> </div>
<div class="line"><a id="l01620" name="l01620"></a><span class="lineno"> 1620</span>    _REG_(M33_PIDR1_OFFSET) <span class="comment">// M33_PIDR1</span></div>
<div class="line"><a id="l01621" name="l01621"></a><span class="lineno"> 1621</span>    <span class="comment">// CoreSight Peripheral ID1</span></div>
<div class="line"><a id="l01622" name="l01622"></a><span class="lineno"> 1622</span>    <span class="comment">// 0x000000f0 [7:4]   DES_0        (0xb) Together, PIDR1</span></div>
<div class="line"><a id="l01623" name="l01623"></a><span class="lineno"> 1623</span>    <span class="comment">// 0x0000000f [3:0]   PART_1       (0xd) Bits[11:8] of the 12-bit part number of the component</span></div>
<div class="line"><a id="l01624" name="l01624"></a><span class="lineno"> 1624</span>    io_ro_32 pidr1;</div>
<div class="line"><a id="l01625" name="l01625"></a><span class="lineno"> 1625</span> </div>
<div class="line"><a id="l01626" name="l01626"></a><span class="lineno"> 1626</span>    _REG_(M33_PIDR2_OFFSET) <span class="comment">// M33_PIDR2</span></div>
<div class="line"><a id="l01627" name="l01627"></a><span class="lineno"> 1627</span>    <span class="comment">// CoreSight Peripheral ID2</span></div>
<div class="line"><a id="l01628" name="l01628"></a><span class="lineno"> 1628</span>    <span class="comment">// 0x000000f0 [7:4]   REVISION     (0x0) This device is at r1p0</span></div>
<div class="line"><a id="l01629" name="l01629"></a><span class="lineno"> 1629</span>    <span class="comment">// 0x00000008 [3]     JEDEC        (1) Always 1</span></div>
<div class="line"><a id="l01630" name="l01630"></a><span class="lineno"> 1630</span>    <span class="comment">// 0x00000007 [2:0]   DES_1        (0x3) Together, PIDR1</span></div>
<div class="line"><a id="l01631" name="l01631"></a><span class="lineno"> 1631</span>    io_ro_32 pidr2;</div>
<div class="line"><a id="l01632" name="l01632"></a><span class="lineno"> 1632</span> </div>
<div class="line"><a id="l01633" name="l01633"></a><span class="lineno"> 1633</span>    _REG_(M33_PIDR3_OFFSET) <span class="comment">// M33_PIDR3</span></div>
<div class="line"><a id="l01634" name="l01634"></a><span class="lineno"> 1634</span>    <span class="comment">// CoreSight Peripheral ID3</span></div>
<div class="line"><a id="l01635" name="l01635"></a><span class="lineno"> 1635</span>    <span class="comment">// 0x000000f0 [7:4]   REVAND       (0x0) Indicates minor errata fixes specific to the revision of...</span></div>
<div class="line"><a id="l01636" name="l01636"></a><span class="lineno"> 1636</span>    <span class="comment">// 0x0000000f [3:0]   CMOD         (0x0) Customer Modified</span></div>
<div class="line"><a id="l01637" name="l01637"></a><span class="lineno"> 1637</span>    io_ro_32 pidr3;</div>
<div class="line"><a id="l01638" name="l01638"></a><span class="lineno"> 1638</span> </div>
<div class="line"><a id="l01639" name="l01639"></a><span class="lineno"> 1639</span>    <span class="comment">// (Description copied from array index 0 register M33_CIDR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l01640" name="l01640"></a><span class="lineno"> 1640</span>    _REG_(M33_CIDR0_OFFSET) <span class="comment">// M33_CIDR0</span></div>
<div class="line"><a id="l01641" name="l01641"></a><span class="lineno"> 1641</span>    <span class="comment">// CoreSight Component ID0</span></div>
<div class="line"><a id="l01642" name="l01642"></a><span class="lineno"> 1642</span>    <span class="comment">// 0x000000ff [7:0]   PRMBL_0      (0x0d) Preamble[0]</span></div>
<div class="line"><a id="l01643" name="l01643"></a><span class="lineno"> 1643</span>    io_ro_32 cidr[4];</div>
<div class="line"><a id="l01644" name="l01644"></a><span class="lineno"> 1644</span>} <a class="code hl_struct" href="structm33__hw__t.html">m33_hw_t</a>;</div>
<div class="line"><a id="l01645" name="l01645"></a><span class="lineno"> 1645</span> </div>
<div class="line"><a id="l01646" name="l01646"></a><span class="lineno"> 1646</span><span class="preprocessor">#define m33_hw ((m33_hw_t *)PPB_BASE)</span></div>
<div class="line"><a id="l01647" name="l01647"></a><span class="lineno"> 1647</span><span class="preprocessor">#define m33_ns_hw ((m33_hw_t *)PPB_NONSEC_BASE)</span></div>
<div class="line"><a id="l01648" name="l01648"></a><span class="lineno"> 1648</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structm33__hw__t.html">m33_hw_t</a>) == 0x43000, <span class="stringliteral">&quot;&quot;</span>);</div>
<div class="line"><a id="l01649" name="l01649"></a><span class="lineno"> 1649</span> </div>
<div class="line"><a id="l01650" name="l01650"></a><span class="lineno"> 1650</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_M33_H</span></div>
<div class="line"><a id="l01651" name="l01651"></a><span class="lineno"> 1651</span> </div>
<div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
<div class="ttc" id="astructm33__hw__t_html"><div class="ttname"><a href="structm33__hw__t.html">m33_hw_t</a></div><div class="ttdef"><b>Definition:</b> m33.h:30</div></div>
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